hi altera
right now i’m having a design that contains a cpu and a maxii epm1270 cpld. the four jtag pins on the cpld are connected to cpu io pins and through those it’s possible to program the cpld via jam-player and that works fine. the design also contains a reset signal which is generated from a power-manager ic which releases the reset signal when all the power supplies on the board are up running. the reset signal is connected to both the cpld and the cpu because there is a watch dog functionality in cpld which may toggle the reset pin to the cpu if some defined event happens. my first worry was if a cpu programming of the cpld was in progress and suddently was interrupted. could the reset pin of the cpld get stocked for example in a low state which would hold the cpu in reset forever. but that seem to be impossible though this statement in maxii userguide Interrupting In-System Programming[/B][/B]
Altera does not recommend interrupting the programming process. However, the
MAX II device has an ISP_DONE bit that will only be set at the very end of a
successful program sequence. The I/O pins will only drive out if this bit is set. This
prevents a partially programmed device from driving out and operating
unpredictably.
my next concern is then: is it possible to connect to the cpld again after an interrupted isp programming via jtag from the cpu and the program the cpld again and get the system up running ?
