The problem of LCD Core

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Hello! 

I am tring to edit a new LCD core,like this.   http://b32.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee91b9b9becdec16dcae957c39d05340496602d68b361471d3c000385a1ada4a41e8741cd93898a3a895c57177e8d70f2cdc77bd34267771336d1f1751edf7e1f00355521b3&a=32&b=32    I want to supply 50M clock frequency to the inclk from outside,and connect the hs,vs,red,green,blue,enable,lcdclk to the LCD.To read data from the FIFO so I connect the ready,writedata,c to the FIFO.   http://b32.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee9d134c640d99150ae0f0b6cff8eeded9abfb61b445eeb874d5ebf349f5ae95c614e27bf1f86c25cd595d3a3c8135c92b0a10a74da97d58a841ed6e211e6170ed4939c8544&a=31&b=32    There are a lot of errors that I cann't solve.can anyone suggest me?   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity displayer is port(inclk:in std_logic; hs: out std_logic; vs: out std_logic; datain:in std_logic_vector(23 downto 0); red: out std_logic_vector(7 downto 0); green: out std_logic_vector(7 downto 0); blue: out std_logic_vector(7 downto 0); ready: out std_logic; c: out std_logic); end displayer; architecture behave of displayer is signal fcounter:std_logic_vector(2 downto 0); signal hcounter:std_logic_vector(8 downto 0); signal vcounter:std_logic_vector(8 downto 0); signal hsync,vsync:std_logic; signal fclk:std_logic; begin process(inclk) begin if(inclk'event and inclk='1')then fcounter<=fcounter+1; end if; end process; fclk<=fcounter(2); process(fclk) begin if(fclk'event and fclk='1')then if(hcounter=408)then hcounter<=(others=>'0'); else hcounter<=hcounter+1; end if; end if; end process; process(fclk) begin if(fclk'event and fclk='1')then if(hcounter=388)then if(vcounter=270)then vcounter<=(others=>'0'); else vcounter<=vcounter+1; end if; end if; end if; end process;   process(hcounter) begin if(hcounter<30)then hsync<='0'; else hsync<='1'; end if; end process; process(vcounter) begin if(vcounter<3)then vsync<='0'; else vsync<='1'; end if; end process; process(hcounter,vcounter) begin if(hcounter>68 and hcounter<388 and vcounter>18 and vcounter<258)then ready<='1'; else ready<='0'; end if; end process; blue<=datain(7 downto 0); red<=datain(15 downto 8); green<=datain(23 downto 16); hs<=hsync; vs<=vsync; c<=fclk; end behave;   thanks in advance!

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li_polaris_1988@yahoo.cn thank you very much!