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How can I split bus in Quartus?

Altera_Forum
Honored Contributor II
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I am trying to split the bus from nios to interconnect with the 4bit counter but I cannot find the way. Is possible? please see the picture!

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Altera_Forum
Honored Contributor II
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Hi Neos 

 

Name the counter bus something like counter[3..0] and then name each of the nodes (QA to QD) counter[3], counter[2], counter[1] and counter[0] 

 

Hope this helps 

 

Best regards, 

Thiago
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Altera_Forum
Honored Contributor II
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Thank you for your reply! 

I wonder if this can be done? 

The counter is the IC component 74192. 

It is taken from the component library. If I double click it I can see the circuit logic... but I don't think that I can do something!
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Altera_Forum
Honored Contributor II
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If I understood the question correctly then do this: 

 

1) From the QA port draw a single line out that doesn't connect to anything and name it "counter[0]" 

 

2) Do the same with the QB, QC, and QD ports and name them counter[1], counter[2], and counter[3] 

 

3) Draw a bus line to the SOPC Builder system that doesn't connect to anything else and name it "counter[3..0]" 

 

Quartus II knows that those individual signals connect to the SOPC Builder system since they share the same name. Alternatively you could just wire the four outputs into a bus line within the counter and not have to worry about doing this in the schematic.
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Altera_Forum
Honored Contributor II
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It worked!  

Thank you very much both of you for the solution!!!
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Altera_Forum
Honored Contributor II
30,442 Views

Thanks so much, this helped me solve my problem too.

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Altera_Forum
Honored Contributor II
30,442 Views

 

--- Quote Start ---  

If I understood the question correctly then do this: 

 

1) From the QA port draw a single line out that doesn't connect to anything and name it "counter[0]" 

 

2) Do the same with the QB, QC, and QD ports and name them counter[1], counter[2], and counter[3] 

 

3) Draw a bus line to the SOPC Builder system that doesn't connect to anything else and name it "counter[3..0]" 

 

Quartus II knows that those individual signals connect to the SOPC Builder system since they share the same name. Alternatively you could just wire the four outputs into a bus line within the counter and not have to worry about doing this in the schematic. 

--- Quote End ---  

 

 

 

Hi BadOmen, I face similar problem so I came across this post: 

 

Instead of creating twelve Parallel input output ports (PIO) in Qsys/SOPC, is there any way I could vectorise many parallel input output ports (12 PIOs for example) into a single component in Qsys or SOPC? 

 

Each PIO consists of 12 bits. 

 

After creating the Nios system, I am going to include the Nios system block in the schematic in Quartus.  

 

I need to feed the twelve PIOs into one single bus line in the schematic block in Quartus II. So I thought I want to combine the twelves PIOs so that in the NIos system block, it will only show one PIO instead of twelve. 

 

I attached the image: 

adc[1..12][11..0] is the 12 signals, each with 12 bits 

in Nios system block, adc_v1_export is single signal, with 12 bits 

 

I want to connect 

 

What I have tried : I followed the advice in this thread but i got the following error (Error (275024): Width mismatch in port "adc_v1_export[11..0]" of instance "inst14" and type nios_system -- source is ""adc[0]""). 

 

Thank you
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Altera_Forum
Honored Contributor II
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The problem is that the 2D bus coming out int8 is getting separated to single wires when they connect to nios_system. When you connect those buses to nios_system use the bus drawing option (thick line) because right now you are trying to funnel 12 wires into 1 which is why Quartus is complaining.  

 

I have never tried round 2D bus lines in a schematic before so I'm not certain what indexing you need to use so you might need to use adc[0][11..0], adc[1][11..0], etc... when connecting to nios_system.
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Altera_Forum
Honored Contributor II
30,443 Views

 

--- Quote Start ---  

The problem is that the 2D bus coming out int8 is getting separated to single wires when they connect to nios_system. When you connect those buses to nios_system use the bus drawing option (thick line) because right now you are trying to funnel 12 wires into 1 which is why Quartus is complaining.  

 

I have never tried round 2D bus lines in a schematic before so I'm not certain what indexing you need to use so you might need to use adc[0][11..0], adc[1][11..0], etc... when connecting to nios_system. 

--- Quote End ---  

 

 

Thank you, BadOmen. you are right and I managed to achieve this, but I am wondering if we could do the opposite? Instead of splitting single line into many signals, how could I merge many signals to single? the reason I am asking is because in the Qsys, I am using twelve input parallel ports (lets name them pio1 to pio12), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio12 from the nios ii system symbol so I can connect these pios to other blocks in my bdf.  

 

My question is, how to vectorize these pio1 to pio12? Instead of seeing all twelve pios one line by one line coming out from the Nios system symbol, what should I do in order to group all these twelve pios so that I only see one instead of twelve? From the one pio that I see, I can name it pio[1..12][1..12], the first bracket means pio1 to pio12, the second bracket means bit1 to bit 12 because each parallel port has 12 bits. 

 

Thank you in advance, appreciate any input
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