Multicycle constraint problems

[Altera_Forum]

I think I may be missing a trick somewhere and I would appreciate any advice. I have an FPGA design which includes PCI and Firewire (S800) interfaces plus an image processing unit. The design works in hardware (Altera Cyclone II PCI development card). But fmax is right on the edge. Some compiles are OK, others are not. I am working on the constraints to improve fmax. All of the external signal constraints are OK so I am concentrating on multicycle and false paths. These are not too difficult to identify but I am having problems in actually specifying the constraints. 

  I have attached a bdf file to illustrate a typical example of the problem as described in the following. The problem is that the nodes from my design are optimized out and replaced with generated nodes which are very difficult to interpret. For example, I have a ram (Ax_RAM:Ax_RAM_inst) which is used to store coefficients. These coefficients are clocked out of the ram (node Ax[63..0]) through a mux (lpm_mux3:inst3) and into the dataa input of a multiplier block (altfp_mult0:inst6). The ram output is registered. There is a one clock delay between the ram data valid and the clk enable of the multiplier. Therefore I set a multicycle constraint of 2 clocks on the path. But the constraint is ignored because the ram output (Ax[63..0]) and the multiplier input are both optimized away. They don't appear in the node finder (post synthesis filter). Digging into the Technology Map Viewer (post-mapping) diagrams, I can find the ram output but the mux and the multiplier seem to have been combined into a unrecognizable unit with very strange inputs. The subject path still exists but I don't understand how to specify it as a multicycle constraint. I am also concerned that if I change the design, the generated nodes will also change. This would make it very difficult to maintain the constraints in the assignment editor.    In fact, in this module, none of my node labels survive synthesis.    If anyone knows how to do this or where to find documentation that explains how to do this in a real design I would appreciate the info.   Thanks, ereeves