ASMI problems

[Altera_Forum]

Hello, 

I'm trying to use the parallel ASMI with cycloneIII and EPCS16 I am not able to read or write from the EPCS16 device. After a lot of tests I found out that the problem is with the line nCSO. It's working in an inverted way, it's at low position at IDLE and at HIGH position during a transition. The other lines are OK: ASDO, CLK   I attached a scope capture of some of the lines: Read - read pulse to the ASMI block (FPGA internal line) busy - output line from the ASMI block (FPGA internal line) nCSO - CS line - the problem line:confused:  ADSI - Data line from the FPGA to the EPCS - working ok (address: x"555")   Did I forget to do someting? Is there a Quartus check box I forgot? Please Help Thanks

[Altera_Forum]

Please update to Quartus 9.1sp1 or Quartus 9.0sp2 and regenerate the ASMI core. 

 And do not forget to set the four ASMI pins (FLASH_nCE/nCSO, Data[1]/ASDO, DCLK and Data[0]) to "Use as regular I/O" in the Dual-purpose pins tab.  I have the exact setup here and it works fine.  What timing are you using ? Please read http://www.alteraforum.com/forum/showthread.php?t=20938

[Altera_Forum]

amilcar, 

Thanks for your quick answer. I tried every thing you said but It didn't work. I upgraded to version 9.1 and regenerated the ASMI_Parallel core. I changed the pins to "Use as regular I/O".   I get the same result.   More about my setup: I use cycloneIII EP3C40 The clock that is connected to the core is only 8MHz   The problem is that all the lines are working correctly but only the nCSO line polarity is wrong   If you have any more ideas please respond Thanks

[Altera_Forum]

I managed to bypass the problem so i'm posting it for future seekers: 

 I changed the ALTERA ASMI core vhd file manually: ----------------------------------------------------------- old code:  PROCESS (clkin_wire, end_ophdly)  BEGIN  IF (end_ophdly = '1') THEN ncs_reg <= '0';  ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN   IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '1';  END IF;  END IF;  END PROCESS; ------------------------------------------------------------ new code:  PROCESS (clkin_wire, end_ophdly)  BEGIN  IF (end_ophdly = '1') THEN ncs_reg <= '1';  ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN   IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '0';  END IF;  END IF;  END PROCESS; -------------------------------------------------------------  now the design is working ;)

[Altera_Forum]

You should report that bug to altera. They fixed the verilog code, but forgot to fix the VHDL code.

[Altera_Forum]

amilcar, 

I just created a new verilog code with 9.1sp1 to see if you are correct, and I'm sorry to say that the code look the same as before. I didn't test it but it look the same as the vhdl code

[Altera_Forum]

pogoking, I am using the ALTASMI_PARALLEL verilog megafuction here and can communicate between my EP3C40 and EPCS16. 

 I can use both megafunctions from QII 9.0sp2 and 9.1sp1. Both versions work fine in hardware and I can even simulate them in modelsim including EPCS simulation.   The only thing that I am missing is the timeQuest constraints, those i still not have them fully correct (http://www.alteraforum.com/forum/showthread.php?t=20938), but the rest works fine.