Netlist writer

[Altera_Forum]

Hi I am using the SOPC builder to create a NIOS based system. I wanted to use an open source tool minSSTA to perform timing analysis. The tool accepts .bench: circuit netlist file 

  - Here is a brief description of format of .bench file: ( from the tools readme file )  It starts by declaring the primary inputs/outputs. As an example,  INPUT(G0) -- 'G0' is a primary input (PI)  OUTPUT(G17) -- the output of gate 'G17' is a primary output (PO).  Since the PO name is not explicitly given, in MinnSSTA, the POs  are named after the gate providing the signal, e.g., POG17. The netlist is described by a set of equation-like descriptions. For example,  G10 = NOR(G14, G11) means that G10 is of NOR-type, and it has 2 inputs which are outputs of G14 and G11, respectively.   So my question is can i get gate level netlist from the quartus tool in any format. I can write a script to convert it  Also I am not able to view the nios cpu in rtl viewer, so if use it in my design will i atleast be able to see its gate level netlist.   Thanks

[Altera_Forum]

--- Quote Start ---  Hi I am using the SOPC builder to create a NIOS based system. I wanted to use an open source tool minSSTA to perform timing analysis. The tool accepts .bench: circuit netlist file   - Here is a brief description of format of .bench file: ( from the tools readme file )  It starts by declaring the primary inputs/outputs. As an example,  INPUT(G0) -- 'G0' is a primary input (PI)  OUTPUT(G17) -- the output of gate 'G17' is a primary output (PO).  Since the PO name is not explicitly given, in MinnSSTA, the POs  are named after the gate providing the signal, e.g., POG17. The netlist is described by a set of equation-like descriptions. For example,  G10 = NOR(G14, G11) means that G10 is of NOR-type, and it has 2 inputs which are outputs of G14 and G11, respectively.   So my question is can i get gate level netlist from the quartus tool in any format. I can write a script to convert it  Also I am not able to view the nios cpu in rtl viewer, so if use it in my design will i atleast be able to see its gate level netlist.   Thanks  --- Quote End ---    Hi,   you can choose under EDA tool setting -> Timing Analysis -> custom.  Quartus writes out a gatelevel netlist and a SDO file. The sdo file contains the timing information. The required libraries for the altera elements can be found under: <Quartus install Dir>\quartus\eda\synthesis.  Kind regards  GPK

[Altera_Forum]

Hi I am using a Nios 2 CPU, will the generated .vo netlist contain primitives describing the CPU as well as it is encrypted.

[Altera_Forum]

--- Quote Start ---  Hi I am using a Nios 2 CPU, will the generated .vo netlist contain primitives describing the CPU as well as it is encrypted.  --- Quote End ---    Hi,  when you use a time limited NIOS version you could not write out a <>.vo file.  Kind regards  GPK

[Altera_Forum]

Thanks for your quick response 

 I am able to generate the .vo file, does this mean that I have the license for the files.  Can I make quartus synthesize the nios2 ip to a simple library instead of fpga primitives. Or is there any eda tool which can take the output from altera synthesis and synthesize the ip into a simpler library of gates. Are the modules provided in eda/sim_lib/stratixiii_atoms.v synthesizabe or are they just functional models which can be used in Model Sim

[Altera_Forum]

--- Quote Start ---  Thanks for you quick response  I am able to generate the .vo file, does this mean that I have the licence for the files.  Can I make quartus synthesize the nios2 ip to a simple library instead of fpga primitives. Or is there any eda tool which can take the output from altera synthesis and synthesize the ip into a simpler library of gates. Are the modules provided in eda/sim_lib/stratixiii_atoms.v synthesizabe or are they just functional models which can be used in Model Sim  --- Quote End ---    Hi,  as far as I know they are only usable for functional simulation.  Kind regards  GPK

[Altera_Forum]

Do you have any suggestions as to what would be the easiest way for me to generate a simple netlist in terms of and, or not primitives from a Nios 2 based design.

[Altera_Forum]

--- Quote Start ---  Do you have any suggestions as to what would be the easiest way for me to generate a simple netlist in terms of and, or not primitives from a Nios 2 based design.  --- Quote End ---    Hi,  I have no idea how you can get your netlist. Sorry.  Kind regards  GPK