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This may be a simple newbie problem, but I am having some difficulty getting my test bench simulation to produce data transitions aligned with the rising edge of the clock in the modelsim wave window.
I am using the DSPBuilder TestBench block to generate and launch a Modelsim-ASE simulation. Data is read from my Matlab workspace through an init function .m file and is applied to the system. The data and clock appear as expected in the Modelsim wave window except that the data is aligned to the falling edge of the clock, not the rising edge. If I was writing a VHDL test bench this could be easily changed by editing the initial state of my clock variable. Here I am using Simulink/Matlab to provide stimulus to my UUT, but I can't seem to find where I can change the polarity of the clock. I have instantiated the "Clock" block from the AlteraBlockset, but it doesn't appear to have parameters to control the duty cycle or phase. -SeanLink Copied
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