Why QuartusII sysnthesis tool interpreting this verilog code as a latch?

Altera_Forum · ‎02-12-2010

I have question about the verilog code causing Latch and not flip-flop. Your suggestions are welcome. I can add more register stage to this but that can affect the performance.

I am not sure why the QuartusII synthesis tool is considering

ReqInFifoDataIn[72] a latch and not a flip-flop? ReqInFifoData[72] is

clearly defined as part of synchronous always block. It is getting

used by wTag signal - Here I am anding the D input of the Flip-Flop

and Qn output of the same D flip-flop. The purpose of this is to

generate one clock wide wTag pulse.

input [81:0] RxStreamData0,

wire wTag = RxStreamData0[72] & ~ReqInFifoDataIn[72];

reg [81:0] ReqInFifoDataIn;

always @(posedge AppClk or negedge PcieRstN) begin

if (!PcieRstN) begin

ReqInFifoDataIn <= 96'b0;

ReqInFifoDataValid <= 1'b0;

ReqInFifoDataVal <= 1'b0;

end

else begin

ReqInFifoDataIn[81:0] <= RxStreamData0[81:0];

ReqInFifoDataValid <= RxStreamValid0;

ReqInFifoDataVal <= ReqInFifoRd;

end

Altera_Forum · ‎02-12-2010

Have you tried separating your assignment from the declaration? Altera may not be supporting all the system verilog style assignments for synthesis.

like this,

wire wTag;

assign wTag = RxStreamData0[72] & ~ReqInFifoDataIn[72];

Altera_Forum · ‎02-13-2010

input RxStreamData0; reg ReqInFifoDataIn; always @(posedge AppClk or negedge PcieRstN) if (!PcieRstN) begin ReqInFifoDataIn <= 96'b0; ReqInFifoDataValid <= 1'b0; ReqInFifoDataVal <= 1'b0; end else begin ReqInFifoDataIn <= RxStreamData0; ReqInFifoDataValid <= RxStreamValid0; ReqInFifoDataVal <= ReqInFifoRd; end wire wTag; assign wTag = RxStreamData0 & ~ReqInFifoDataIn;

Altera_Forum · ‎02-14-2010

--- Quote Start ---

input  RxStreamData0;
reg  ReqInFifoDataIn;
always @(posedge AppClk or negedge PcieRstN)
  if (!PcieRstN) 
  begin 
    ReqInFifoDataIn    <= 96'b0;     ReqInFifoDataValid <= 1'b0; 
    ReqInFifoDataVal   <= 1'b0; 
  end 
  else 
  begin 
    ReqInFifoDataIn <= RxStreamData0; 
    ReqInFifoDataValid    <= RxStreamValid0; 
    ReqInFifoDataVal      <= ReqInFifoRd; 
  end 
  
 wire wTag;
 
 assign wTag = RxStreamData0 & ~ReqInFifoDataIn;

--- Quote End ---

Hi,

the reason could be your reset initialization. You are trying to set 96 bit to "0", but your reg vector is only " reg [81:0] ReqInFifoDataIn;"

Kind regards

GPK

Altera_Forum · ‎02-15-2010

J'ai conçu un circuit sous quartus II et je veux le validé par un fichier de données élaborer par un programme en langage C, et récupérer les sorties sous forme d'un fichier text, comment faire?

Altera_Forum · ‎02-16-2010

Sorry, I do not well in French.