Verify problem while runing on Nios II hardware

[Altera_Forum]

Hi there, 

 when i try to run my project on the Nios II hardware i get the following problem:  Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Reading System ID at address 0x00070000: verified Initializing CPU cache (if present) OK  Downloading 00080000 ( 0%) Downloaded 43KB in 0.7s (61.4KB/s)  Verifying 00080000 ( 0%) Verify failed between address 0x80000 and 0x8ABDF Leaving target processor paused  I use the SRAM memory on DE1 board which has the Cyclone II FPGA. I also checked the base and end address for SRAM, and there is also no overlaping. The SRAM memory has the base address 00080000 and 0008ffff end address. I also use the on-chip memory for better perfomance. Have anyone an idea how to fix that problem?   Best regards!

[Altera_Forum]

Check your timings, both in SOPC builder for the SRAM and in Timequest when you compile the Quartus project. 

You can also compile a memory test example, run it from the on-chip memory and have it test the SRAM.

[Altera_Forum]

check in pin planner, positions of 

1 reset 2 clock  check in system library properties that you are using on chip memory as program memory