avalon fifo issue - module dependency loop

[Altera_Forum]

I have an Avalon ST-MM FIFO implemented in SOPC. After programming the FPGA, the first time I use NIOS to touch the FIFO CSR (init, clear, read, or whatever) the system hangs. If I then stop the NIOS and rerun the program, it runs through without a hitch. When I reprogram the FPGA, it repeats this behavior. The FIFO is on a Pipeline Bridge, and I have noticed a warning in SOPC that there is a "Module dependency loop" involving the Bridge and the FIFO. I can't seem to find any documentation about what that means exactly or its implications. Anybody got any suggestions? Thanks.

[Altera_Forum]

Hi coverman,  

I got the same issue but between Altera_UP_SD_Card_Avalon_Interface_0 and DDR SDRAM Controller. Do you have solution now??

[Altera_Forum]

Hi all, I solved it by changing frequency in SDRAM controller. My Core(Cyclon IV) does not support the last frequency. Thanks for reading!