Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus switch to keep all logic

Altera_Forum
Honored Contributor II
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I am trying to compile a very large design block per block, the complete design will not fit in one FPGA .  

 

Is there a way: 

1. To tell Quartus not to remove any logic even if inputs are floating and outputs have no loads? 

2. To load the complete design and tell Quartus to synthesize it irrespective of the size? 

 

Thanks
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Altera_Forum
Honored Contributor II
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If your design is too large to fit into the selected FPGA, synthethizing it block by block won't help you. You need to 

a) optimize you design 

b) try a better tool (ie, Synplify) 

c) get a bigger FPGA 

 

If you're just trying to synthetize each block to understand how many resources and why it's taking, just set each block as top level and synthetize the design.
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Altera_Forum
Honored Contributor II
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i'm not quite sure what you're trying to do, but virtual pins may help with# 1. see page 35: 

 

http://www.altera.com/literature/hb/qts/qts_qii51015.pdf
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