Clock necessary under Boundary Scan control?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Clock necessary under Boundary Scan control?

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I intend to control the I/O pins of the EPM7032AETC44-10N cpld via boundary scan. Do I still need to provide a clock signal, or, make connections of some sort (pull-ups, pull-downs, etc.) to the GCLK1, GCLK2, GCLRn and OE1n pins? Or, can I leave them unconnected?

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