bursts with NIOS II and avalon-mm clock crossing bridge

[Altera_Forum]

My prob.: I have to store small data at high speed at the ddr ram(up to 20-160 bytes of data every 100µs). 

So maybe I need bursts. Just have to be fast when I write. The reading time doesnt bug me at all.  Now my question: Does the burst support of the avalon-mm clock crossing bridge help me? Do I have bursts at all when I use the IOWR Macro?  I would use a burst length of 8(Whis would fit best for my application).  I use a NIOS II/F cpu with 2k inst. cache and 512bytes data cache. d-ram and i-ram @ on-chip memory. Got connection to 2 DDR2 SDRAM HIGH Performance Controllers over 2 Avalon-MM Clock Crossing Bridnges for storing datas. Got a Stratix III device.

[Altera_Forum]

You won't have bursts using the IOWR macro because it does a single write operation. To have bursts you need to either use a DMA engine that supports bursts, or have the CPU write to its data cache (using traditional pointers) and force it to dump the cache when finished.