Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16597 Discussions

LVDS Tx drive strength and slew rate?

Altera_Forum
Honored Contributor II
‎02-17-2010 06:00 PM
1,151 Views

I'm trying to clean up some of my compilation warnings and one I don't quite understand is "Some pins have incompelete I/O assignments ..." When I go the "I/O Assignment Warnings" report, the only pins listed are my LVDS TX pins. I tried going to the Pin Planner and see if I could change the settings, but I only get "Maximum Current (default)" option in the drive strength and the slew rate is blank. What should I specify in the QSF to get rid of the warning? 

 

Thanks
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎02-17-2010 08:32 PM
338 Views

There are no editable parameters for LVDS outputs. The "incomplete I/O assignments" warning is usually given together with these:  

 

--- Quote Start ---  

Warning: Pin "LVDS1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LVDS1(n)" 

--- Quote End ---  

 

The fitter reminds you to check, if you selected the correct (n) pins for differential pairs.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.