- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'm having an issue with programming a board through PCIe. I've been following the CvP Driver Flow document and the issue I run into is that in the 'Teardown' part of the process the CVP_CONFG_READY bit is always set to 1. The bit will does not change and I am unaware of how to change it. If I were to skip over the condition the same issue happens with the PLD_CLK_IN_USE and the USER_MODE bits. Both are set to 0 and does not ever appear to change. Any assistance would be greatly appreciated.
Link Copied
0 Replies
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page