How change the memory size in PCIe Hard IP

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How change the memory size in PCIe Hard IP

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I have successfully generated the Altera stratix4GX PCIe gen1 x4 HardIP example using PCIe compiler software using megawizard flow. It contains the following BARs

(1) BAR0, BAR1 - Contains 64 bit prefetchable memory that can support upto 4GByte of memory

(2) BAR2 - Contains 32 bit non-prefetchable memory that can support upto 256KByte of memory.

I would like to change the BAR0 and BAR1 to support much lower size may be 256MBytes of memory. I am not sure how to change this without regenerating new one from PCIe compiler using megawizard flow. At this point I have made some changes to the design to talk to the hard IP using Avalon Streaming interface.

Your suggestions are welcome.

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