Error(11999): Channel(s) under reference clocks - arria 10 development kit design

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Error(11999): Channel(s) under reference clocks - arria 10 development kit design

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I'm designing a system on an Arria 10 development kit which uses the FMC connectors as I/O, and have assigned pins according to the user guide. The design passes analysis and synthesis, however I receiving this error on the fitting stage of compilation:

error(11999): channel(s) under reference clocks: are 50 tx channels, 0 rx channels, which exceeds the capacity for the targeted device's hssi strip, 36 channels.

Any ideas on why this is the case if this board has been designed in the this way, or ideas on how to rectify this?

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