Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Powerplay Result

Altera_Forum
Honored Contributor II
1,090 Views

Hi,I have generated a .vcd file and insert it into the Powerplay Power Analyzer Tool in Quartus II 11.0,and get the result as follow. I think the dynamic power is too small. IS THIS RESULT CORRECT? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13694&stc=1  

And I think there may be sth wrong about the clock, I show the warnings in the following and HOW CAN I CORRECT IT. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13695&stc=1  

 

thanks sincerely.
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Altera_Forum
Honored Contributor II
379 Views

Hello, 

 

From waht I read, I think Quartus does not have enough info to conclude anything. 

In the SDC file you might need to update/correct your clock timing constraints. 

 

Best Regards, 

Johi.
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Altera_Forum
Honored Contributor II
379 Views

 

--- Quote Start ---  

Hello, 

 

From waht I read, I think Quartus does not have enough info to conclude anything. 

In the SDC file you might need to update/correct your clock timing constraints. 

 

Best Regards, 

Johi. 

--- Quote End ---  

 

 

Thanks for your reply. 

And can you tell me how can I set timing constraints? Is it be set in the timequest in Quatrus timing analyzer? 

 

Thanks sincerely.
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Altera_Forum
Honored Contributor II
379 Views

You should have a .sdc file that includes timing constraints for your design, which is listed in the screenshot, so I'm not sure if you got that .sdc from somewhere else or created it yourself. See the Quartus handbook and online trainings like this for details: 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=timequest
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