Dear all,
i'm new to HW/SW modeling and verification. i've been trying to follow a tutorial to simulate a multiprocessor enviroment
I don't have a board so i thought that it might be possible to run it on modelsim.
I have done all the steps to create the model and i've build the software model on the ide.
Then i opened a Nios II shell command
and run vsim setup_sim.do
then on the modelsim i follow these steps:
"s"
"w"
"jtag_uart"
run 800 us
the simulation starts and i get this message:
Note: Stratix II PLL locked to incoming clock
# Time: 110 ns Iteration: 0 Instance: /test_bench/dut/the_pll/the_pll/altpll_component/stratixii_altpll/m1
# 2410 ns: ERROR: cpu1_test_bench/M_en is 'x'
# ** Failure: VHDL STOP
# Time: 2410 ns Iteration: 11 Process: /test_bench/dut/the_cpu1/the_cpu1_test_bench/#MERGED#line__795,760,704,686,649,613,595,577,521,465 File: C:/Projet_Nios_Modelsim/projet_nios_modelsim_multiprocessor/standard/cpu1_test_bench.vhd
# Break in Architecture europa at C:/Projet_Nios_Modelsim/projet_nios_modelsim_multiprocessor/standard/cpu1_test_bench.vhd line 588
can anyone help me to find the solution ?
Thank you
