Stop Pin Not Connected Warning

[Altera_Forum]

I have a few input pins on my top schematic which are mapped to pins on a Cyclone III FPGA, but which I have not connected to any logic. Quartus gives me a warning 'Pin "..." not connected.' for each of those pins. That's fine, I excepted that, but now I want to know if there is anything I can do to suppress those warnings. I want a way to tell Quartus that I know these pins are unconnected, and that that is intentional. 

 So, is there anything I can connect those pins to to suppress the warnings?

[Altera_Forum]

now that i reread your question i don't think this quite answers it, but... 

 you can right click a message, go to Suppress => Suppress All Similar Messages

[Altera_Forum]

thepancake: That is indeed not the right answer I am looking for, but certainly good information to know! I might use it on a few of the unimportant messages. 

 To clarify, I don't want to suppress all those warnings. I do want to be warned of unconnected pins that I am not aware of. However, if I see one of these warnings, and satisfy myself that the disconnection is intended, I would like to disable the warning for that specific pin. Otherwise the warnings screen is going to fill up with useless information and it will be difficult to sort out the frivolous items from the important ones.

[Altera_Forum]

in that case suppress the exact message rather than all similar messages.

[Altera_Forum]

You can suppress a specific message? Interesting, I'll check that the next time I'm at my workstation. In the meantime, is there no solution I can put into schematics or Verilog files? 

 In C, you can do:  (void)some_unused_parameter;  To stop the compiler from warning you that a parameter (or variable) is unused. I am wondering if the Verilog specifications, or even the compilers specific to Quartus, have something similar.  Thank you for the help so far, by the way.

[Altera_Forum]

I think, the only way to supress the warning for specific pins is to actually connect logic to it. It only works, if you can afford to use at least one pin as logic output, e.g. 

outpin <= inpin1 OR inpin2 OR inpin3; If no output depends on the inserted dummy logic, it will be removed by the design compiler and you get a warning as well. There may be another solution by connecting the dummy logic output to a signal declared "virtual", but I didn't test. I must admit, that I don't have this kind of problems, because I accept to get plenty of warnings for various things. But I basically understand the idea of sorting out all meaningless warnings to see the serious ones.

[Altera_Forum]

FvM: i tried the virtual pin approach, it does not suppress the warning.

[Altera_Forum]

in that case suppress the exact message rather than all similar messages.

[Altera_Forum]

FvM: i tried the virtual pin approach, it does not suppress the warning.