I'm using Quartus II 9.0 Web Edition.
Verilog code:
...
input wr_in, rd_in;
inout [31:0] DATA, DATA_IN;
assign DATA = (!wr_in)? DATA_IN: 32'hzzzzzzzz;
assign DATA_IN = (!rd_in)? DATA: 32'hzzzzzzzz;
...
During compilation I'm getting error message:
Error: The tri-state buffer "ssram_cnt:inst1|DATA[31]" feeding the pin "data[31]" directly or indirectly feeds itself.
data[31] is I/O pin connected to DATA[31]
Not sure what's wrong with this code as I have seen the same example from Altera for CycloneIII starter board.
Any help would be highly appreciated.
