DDR3 SDRAM controller with Uni PHY, DMA and external UART(RS232) qsys implementation

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

DDR3 SDRAM controller with Uni PHY, DMA and external UART(RS232) qsys implementation

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Hi,

I am using MAX 10 FPGA development board (package : 10M50DAF484C6GES). I'm planning to test the memory_test (includes memory test, DMA and FLASH) application in NIOS II. I made a qsys design to test the memory and DMA. I used external UART (RS232) to print the output (I didn't use JTAG UART). I'm using putty as serial terminal. After downloading the .elf on hardware it was stucking. I'm not able to type anything on putty. I'm adding qsys design. If any mistakes is there please let me know.

Thanks in advance.

Regards,

Vijji

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