internal differences in fpga when using sstl_2(or sstl_18) class i and ii io standard

[Altera_Forum]

i am using cyclone ii fpga to interface to ddr ram. by the handbook of cyclone ii, it's top and bottom banks support sstl_2 class i and ii io standards. 

so what's the internal differences(just at the output buffer) in fpga between these two standards. by the circuit(fig 10-1, fig 10-2) of handbook of cyclone ii, class ii differs class i with just an added parallel termination at the source side. if it just means that, at the output buffer of fpga, when i choose class ii io standard, fpga would automatically adds a parallel termination resistor; or it just means that when using class i or ii standard, only the pin's output current differs.   fig 10-1 and fig 10-2 are copied in the attachment.   thanks.

[Altera_Forum]

Altera FPGAs have no separate series termination resistors for SSTL I/O standards, all OCT (on-chip termination) schemes are achieved by activating a combination of output transistors. In so far, series termination is just another name for current strength. You can calculate the effective series termination yourself from the respective IBIS files, that tabulate output characteristics for all I/O standards. 

 For most FPGAs, a 50 ohm series termination with SSTL class I and 25 ohm with class II is given, see e.g. Table 1 in AN408. There seems to be some confusion however with Cyclone II, the above schema shows 25 ohm for both standards, while the datasheet text tells about 50 ohm series OCT in one place and 8 versus 16 mA current strength in another. Clearly, 8 mA involves a different effective series impedance than 16 mA.  As in the AN408 examples, choosing 16 mA respectively 25 ohm with SSTL class I can result in a better signal quality and higher error-free memory clock frequency in some applications. It's good to follow the general sugggestion in a first step and check optimal settings for the individual system later.

[Altera_Forum]

Thank you for your detailed explanation. 

 so, you means fpga changes the effective resistor value by adjusting the output current. as to the sstl_2 class i and ii io standard, first, the output voltages are equal, so different output current results in different effective output resistor value. according to the pin assignments result in quartus, when choosing class i, the default current is 10ma, while class ii is 18ma(for sstl_18, sstl_2 is similar). by the transmission line theory, the resistors are used to enhance SI. as you say, class i's effective resistor is 50ohm, while class ii is 25ohm, then the external series resistor should be accordingly adjusted. if the transmission line characteristic resistor is 50, then class i needs no external series resistor and class ii needs an extra external 25ohm series resistor, is that right?   by the fig 10-1 and fig 10-2(see my original msg), class i and ii effective output resistor value should all be 25ohm.   well, i got confused by the handbook. i will just put an external resistor in there, and adjust its value then.   at last, i want to confirm your point again. "as to sstl_2(sstl_18) class i and ii io standard, they differs mainly in output current(which results in different effective resistor), there is no real series or parallel resistors."   thanks a lot.

[Altera_Forum]

No SSTL interface circuit uses external series resistors. They always rely on the internal driver impedance. It should be also mentioned, that most SSTL interface variants don't achieve exact impedance matching. It's important to have some termination to avoid multiple reflections. The best solution would be dynamic OCT at both sides, but it's not available for Altera FPGAs below Stratix III.

[Altera_Forum]

an408 and your explanation clear me a lot of questions. 

thanks a lot.   there are still some points i am not sure. in an408, it always says '... when the oct on the fpga is turned on'. so what's the meaning of 'oct is turned on'? accordingly to your explanation, the oct should be always there. what else should i do besides setting the output current to turn on the oct? or can the oct be turned off?   if the odt is turned on with a series resistor on the ddr2 side, whether or not there has oct on the fpga side is of little siginificance to me. so if the oct canbe turned off, i will just turn it off.   another point is that if class ii differs class i mainly in output current, and at the same time if i turn on the odt, i will nodoubtly choose class ii for its stronger drive capetence. you says it will be better to use 16ma in class i, do you mean the same thing? if it is, why not choose class ii directly?

[Altera_Forum]

already find the answer from previous threads. 

appreciate your help.

[Altera_Forum]

Two remarks anyway: 

 "Turning on" OCT at the FPGA side is refering to dynamic OCT with Stratix III etc.  Using 25 ohm OCT respectively 16 mA with SSTL class I results in an impedance mismatch, so I won't generally suggest it. But it can be helpful to improve the usable RAM speed in some cases, at least for short FPGA-to-RAM connection lengths.