Very different simulation results of a simple counter

Altera_Forum · ‎03-01-2010

Hello

I'm in my third year bachelor electronics and i'm making a project in vhdl. In this project there is a simple counter that should start counting at zero. The counter has 4 selection outputs for a multiplexer. When i select a cyclone 1 EP1C6Q240C6 the counter counts like it should, it starts at 0000. When i select a cyclone 3 EP3C40F324C8 it almost starts at 0001. It doesn't stay on 0000 long enough. It looks like it reacts way before it gets his clockpulse. And this is causing problems because my multiplexer doesn't output the first bit.

How come that it works like it should with the cyclone 1 and not with the cyclone 3? They both have a clockspeed of around 402MHz. (I have to use the cyclone 3).

In the attached pictures the counter variables are C0, C1, C2 and C4. (There are also glitches noticeable although i enabled glitch filtering)

This is the code of my counter :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

port(C : in std_logic;

Q : out std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0):="0000";

begin

process (C, tmp)

begin

if (tmp="1001") then

tmp <= "0001";

elsif (C'event and C='1') then

tmp <= tmp + 1;

end if;

case tmp is

when "0001" => Q <= "0000";

when "0010" => Q <= "0001";

when "0011" => Q <= "0010";

when "0100" => Q <= "0011";

when "0101" => Q <= "0100";

when "0110" => Q <= "0101";

when "0111" => Q <= "0110";

when "1000" => Q <= "0111";

when "1001" => Q <= "1000";

when others => Q <= "0000";

end case;

end process;

end archi;

Are there any settings of the cyclone 3 i'm overlooking?

Thanks in advance.

Altera_Forum · ‎03-01-2010

I would put those lines:if (tmp="1001") then tmp <= "0001"; inside the clocked event. I'm not sure how the synthesizer will read your code, but it could identify those two lines as an asynchronous reset.

Keep everything synchronous and it will work better.

Is there any reason why you want to keep an internal counter and put its value minus one on the output?

Altera_Forum · ‎03-01-2010

The reason for it is because i want the counter to start at 0000 on the first clockpulse. The counter is connected to a multiplexer and i want it to start at the beginning. Now the counter will count to 0001 on the first pulse but on the output i put 0000. Maby there are better ways to do this, my vhdl knowledge is rather limited actually.

I will try to change the reset, thank you.

edit : I can't belive it, the reset was the problem. I thought it had nothing to do with it. The fact it worked good on the cyclone 1 made me confused.

Thanks alot for your help!

Altera_Forum · ‎03-01-2010

The synthesisor usually takes the asynchronous reset value as the power up state rather than the initial assignment you have given it.

Altera_Forum · ‎03-01-2010

Also, because you've set the asynch reset to be a version of itself, its unlikely to reset itself properly as I guess it wont hold the reset value long enough. Just use a synchronous reset instead:


if (C'event and C='1') then 
  if tmp = "1000" then
    tmp <= "0000";               
  else
    tmp <= tmp + 1;
  end if;
          end if;

Altera_Forum · ‎03-01-2010

I changed the reset in all my counters. The whole schematic works flawless now. Thank you all for your help.

Good to know an asynchronous reset has influence on the power-up state.

Altera_Forum · ‎03-02-2010

it is a good end.....