Color Plane Sequencing

[Altera_Forum]

Hello,  

 I'm trying to utlize the Median Filter in SOPC. I've managed to connect a Clocked Video Input module to a Clocked Video Output Module no problem and pass-thru video data. So CVI -> CVO works great.   However, as shown in the attached picture, I'm trying to alter what I had already working by doing the follwing:   CVI -> Color Plane Seq. 3/1 -> Median Filter -> Color Plane Seq. 1/3 -> CVO.   When I compile and build, nothing happens, I get no SYNCs, nothing. What could be wrong? Assuming I have the sequencers correctly configured, what am I missing here?   Thanks in advance, Mike

[Altera_Forum]

Are you sure your clock rate is high enough? The section of the VIP chain where the video planes are in sequence will require a higher clock rate than when everything is parallel.

[Altera_Forum]

--- Quote Start ---  Are you sure your clock rate is high enough? The section of the VIP chain where the video planes are in sequence will require a higher clock rate than when everything is parallel.  --- Quote End ---     Actually - no, I'm not sure what the clock relationships should be...    Where would I vary the clock rate? At the output of the CVI and the input of the CVO? Should the CVO Input/CVI Output clock be 3x the video clock rate?   Architecturally, does it make more sense to split the data into R,G,B for Median Filter processing?    Thanks, Mike

[Altera_Forum]

The following configuration seems to work correctly: 

 Test Pattern (seq. RGB) -> Median Filter -> Color Plane Seq. (Par. RGB) -> Clocked Video Output (Par. RGB)   With the following clocking:   Test Pattern = 3x video clock Median Filter = 3x video clock Color Plane Seq. = 3x video clock CVO = 1x video clock   I get a nice test pattern out of the above.   Ok, so now I put the following into the data chain   CVI (par. RGB) -> CPS (seq. RGB) -> Median Filter -> CPS (par. RGB) -> CVO (par RGB)   With the following clocking:   CVI = 1x video clock Color Plane Seq. = 3x video clock Median Filter = 3x video clock Color Plane Seq. = 3x video clock CVO = 1x video clock   And this design fails - no switching on any of the video outputs at all, HSYNC, VSYNC and Valid all dead.   I would think its because the CVI -> CPS clocking is somehow incorrect where we would want the CPS to run at 1x video clock when going from parallel RGB to sequential RGB. What is the correct thing to do here as I cannot modify the CPS clock in the SOPC to account for this discrepancy.   Thanks, Mike

[Altera_Forum]

The avalon streaming clock should be the same for each VIP component that is connected together, including the CVI and CVO. Based on your SOPC builder screen shot, all your VIP components are using the same clock, "vid_clk". 

 The CVI and CVO components use two clocks each. These components basically convert the video from one clock domain to another.  The avalon clock for each VIP component does not need to be directly related to the input/output video clock. You could try a clock higher than 3x your video clock.