ALTLVDS megafunction registered outputs/inputs

[Altera_Forum]

Hi, 

 I am learning the ALTLVDS mega function using CIII. I had a question about how ALTLVDS register in/out options works. And a general best practices on when to use register input and outputs option and when not to use the option.  The help doc examples make sense to me when it turns OFF the registered in/out option, and manually insert a register that connects to a slow clock. This makes sense to me to have a fast bit clock and slow frame clock.  What doesn't make sense to me when I turn ON the register in/out option. In this case the mega function appear to register the frame in/output without the need for the slow frame clock as an input to the block. I can only make two guesses. Guess# 1 the megafunction goes behind my back are attempts to find a free PLL output to generate a slow frame output clock for its own use, or it divides the high speed bit clock down using soft logic. Either way it seems more controlled to use have the user specify the frame clock.   I would like to know how the register output option clock is generated.  Or am I miss reading the docs.

[Altera_Forum]

alt_lvds rx_inclock must have frame clock rate or an integer part of it, otherwise the receiver won't be able deserialize the input stream to words.

[Altera_Forum]

Thank Fvm for responding. After some more chats with others I understand that when not selecting the use external pll option, it is implied that a internal PLL resource will automatically be used.  

 Although I'm new to this, it doesn't seem very useful to let Quartus automatically use a PLL. In most cases, the user design will use up one PLL to generate the LVDS clock rate. (This assume clock is @ high speed- IE they will have to use a PLL to multiply the clock crystal up) So it doesn't make sense to me to let the ALTLVDS megafunction automatically consume another PLL when the 1st PLL can generate both the fast clock and slow frame. Also it doesn't feel right when a mega function takes a hard resource automatically. I perfer to instantiate each hard ip resource manually so I know each time a PLL is used. I supposed you could reverse engineer what PLL were used by compiling a design and they looking at what resources were used, but I find this backwards way of doing things.  Does it sound like I am making sense? Thanks for any feedback.

[Altera_Forum]

The basic point is, that LVDS can't work without a PLL, that generates fast and slow clock with matching phases. In some cases, it's necessary to use an separate PLL, e.g. when the LVDS clock isn't derived from the system clock but received from an external source. In this cases, the "internal" PLL variant is obviously preferable for it's ease of use.  

 In other cases, the PLL resources can be shared with system clock generation. If I remember right, Quartus shares it automatically, if possible.  Generally, when planning a design, you have to think about required resources, e.g. PLL count. If Quartus thinks, it doesn't work as intended, it will tell.

[Altera_Forum]

Dear all, 

 Sorry for asking other questions about ALTLVDS using this thread. Currently I'm working with Stratix IV. My current task is to connect the Stratix IV with a DSP board (The DSP board acts as a transmitter, meanwhile the Stratix IV as a receiver). The I/O connection between these two boards using LVDS. The LVDS signals consist of 4 parallel data signal , 1 synchronization signal, and 1 clock signal (150 MHz). The maximum wanted data rate is 600 Mbps.  Well, since I'm a newbie :( in this field, I have some basic questions about LVDS.  

1. When do we choose to use SERDES feature in ALTLVDS? I'm confused about this. :confused: Suppose I choose to use SERDES, it means I have to implement the similar SERDES function in the DSP board, right? All I want to do is just a normal LVDS connection, so I think I don't need to implement this SERDES function, is it correct? 
2. If I choose to not implement SERDES (deserialization factor = 1), the MegaWizard shows that for ALTLVDS_RX only has input and output channels, without any clocks or input/output registers, for my design case is it OK to implement ALTLVDS with such configuration? So for my design case, the ALTLVDS module will only have 6 input and output channels. 
3. Is it correct that the 'channel' term in the ALTLVDS means the LVDS pair signal? If it is yes, in the verilog code do I only need to define the positive signals? Because in the pin assignment the Altera document said that I only need to define the positive signal for LVDS case and for the negative pins will be automatically found and connected by Quartus. 
4. If I want to simulate the behavior of my ALTLVDS, is it enough to only define the positive signals in my testbench without any negative signal definition? Please tell me, if you know how is the proper way to verify the ALTLVDS. 

  That's all my question. Please kindly to help me to answer them. Thank you!

[Altera_Forum]

If you don't use serialization/deserialization, in other words, transmit one signal per LVDS pair, you don't need the ALTLVDS MegaFunction at all. Simply assign LVDS I/O standard to the respective pins, and you're done.

[Altera_Forum]

Ah I see.. I thought that we need to use ALTLVDS in stratix iv just like ALT_INBUF_DIFF primitive in stratix iii / cyclone iii. So in the verilog code the LVDS signal can be read by only reading the positive signal right? 

 Ok so I only need to assign the respective pins correctly in pin assignment. Then, how about the differential on-chip termination? Is it automatically implemented when I assign LVDS pins in the pin assignment?  Thanks