Signal Integrity Issue

[Altera_Forum]

Hi, 

I am having a small issue with a stratix II device regarding a 10MHz I am using in an SPI Interface.   Basically I have a 10MHz clock entering the FPGA and it seems with a small amount of noise. This clock enters on a dedicated clock pin and is then routed to an output pin and connected to the SPI clock pin of a Digital to Analog converter (DAC5687). When the clock exits the FPGA, it has more pronoucned noise, so much so that the SPI serial port of the DAC detects 2 edges where only one has occured.   Please have a look at the attached files. The 10Mhz input (LVPECL) is shown on a 2V/div scale and the signal leaving the FPGA (signle ended) bound for the DAC is also attached (with the same 2V/div scale).   Can anyone tell me what could be the cause of this issue?   My own guesses were that the input signal (attached) which is measured very close to the output of the buffer (no other place to probe it) gets noisier closer to the input of the FPGA and the FPGA detects 2 edges, but then I thought that when this signal then leaves the FPGA it should be cleaner while being twice the frequency of the input.   My second guess was that it was to do with an impedence mismatch. I dont remember reading anything in the DAC datasheet about this, bit even at such a low frequency could this be an issue? I then began to think that the impedance could not be a probelm because I generated another 10MHz clock from a PLL and it worked perfectly, a very clean signal was observed leaving the FPGA.   So I was hoping you guys could give me some more ideas as to what the issue may be.   I also should have said that this issue occurs with an ADC also when I use this clock to configure it via the SPI. Also I should say that this problem is intermittent, sometime I manage to configure the converters and sometimes not, but the clock is never clean. The same clock goes to another FPGA closer to the buffer and I do not have any issues with this clock, it exits the other FPGA very cleanly. I observe the same issue on more than one prototype board we are doing.   Many thanks for any suggestions

[Altera_Forum]

--- Quote Start ---  Hi, I am having a small issue with a stratix II device regarding a 10MHz I am using in an SPI Interface.   Basically I have a 10MHz clock entering the FPGA and it seems with a small amount of noise. This clock enters on a dedicated clock pin and is then routed to an output pin and connected to the SPI clock pin of a Digital to Analog converter (DAC5687). When the clock exits the FPGA, it has more pronoucned noise, so much so that the SPI serial port of the DAC detects 2 edges where only one has occured.   Please have a look at the attached files. The 10Mhz input (LVPECL) is shown on a 2V/div scale and the signal leaving the FPGA (signle ended) bound for the DAC is also attached (with the same 2V/div scale).   Can anyone tell me what could be the cause of this issue?   My own guesses were that the input signal (attached) which is measured very close to the output of the buffer (no other place to probe it) gets noisier closer to the input of the FPGA and the FPGA detects 2 edges, but then I thought that when this signal then leaves the FPGA it should be cleaner while being twice the frequency of the input.   My second guess was that it was to do with an impedence mismatch. I dont remember reading anything in the DAC datasheet about this, bit even at such a low frequency could this be an issue? I then began to think that the impedance could not be a probelm because I generated another 10MHz clock from a PLL and it worked perfectly, a very clean signal was observed leaving the FPGA.   So I was hoping you guys could give me some more ideas as to what the issue may be.   I also should have said that this issue occurs with an ADC also when I use this clock to configure it via the SPI. Also I should say that this problem is intermittent, sometime I manage to configure the converters and sometimes not, but the clock is never clean. The same clock goes to another FPGA closer to the buffer and I do not have any issues with this clock, it exits the other FPGA very cleanly. I observe the same issue on more than one prototype board we are doing.   Many thanks for any suggestions  --- Quote End ---    Hi,  maybe I'm wrong, but in the first picture the timescale is 20ns/div. So it looks like that you are running at 50 MHz ????  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,   maybe I'm wrong, but in the first picture the timescale is 20ns/div. So it looks like that you are running at 50 MHz ????   Kind regards   GPK  --- Quote End ---       This was due to an error when I saved the screenshot. I initially saved it some strange format that I couldn´t open on the PC so I then went back, opened the same file and resaved it as a jpeg. It seemed to have taken the current time/div setting, which wasn´t the same as when the original was captured.  It´s definately a 10MHz signal. Sorry for the confusion