Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12600 Discussions

Is there a avalon master interrupt receiver template?

Altera_Forum
Honored Contributor II
1,555 Views

Is there a avalon master interrupt receiver template? 

 

thank you!
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
332 Views

In component editor there it. It'll generate the .tcl file for one and export them to the top level. You could use that to figure out what you need and make the same settings if you have your own master HDL with an interrupt input ready to go.

0 Kudos
Altera_Forum
Honored Contributor II
332 Views

Is like this one?

0 Kudos
Altera_Forum
Honored Contributor II
332 Views

In order for the DMA to work with the UART you would have to enable Avalon-MM flow control. This is a depreciated feature so I would just stay away from it. Normally people will hook up the UART to Nios II so that it can service the interrupts. The UART that ships with SOPC Builder doesn't buffer data so using a DMA might be overkill for what you are attempting to do. 

 

I think the Nios II driver for the UART always checks that there is valid data in the rx holding register or that there is room for more data in the tx holding register. A simple DMA is not capable of these control based decisions. You could make a statemachine with a master connected to it to do this for you if you are not using Nios II in your system. 

 

I recommend listing out what you are attempting to do so that we can give you more ideas.
0 Kudos
Altera_Forum
Honored Contributor II
332 Views

I want to display a image on the LCD through my LCD_CORE,in my design the SRAM is used as frame buffer,so I must to send the data of a image to the SRAM. 

 

I used to use the UART to receive the data,and the DMA read it and write that to the SRAM when there is an interrupt generated by the UART,but the data is stored in the high 8 bit of the SRAM everytime.So I want to edit a component which is used to buffer the data. 

 

I imagine that the component read the data from the UART when there is a interrupt generated,the component combine two 8bit data to a 16 bit data and generate an interrupt when the component achieved that.then the DMA read the 16 bit data from the component and write it to the SRAM. 

 

I am not sure it is right. 

 

thank you very much!
0 Kudos
Altera_Forum
Honored Contributor II
332 Views

There is a FIFO'ed UART in this forum that I would recommend using since you are sending a lot of data. The standard UART in SOPC Builder does not contain buffers so it can only move a character at a time. 

 

Also you might find system console and the JTAG to Avalon bridge to be more efficient at moving bulk data around. A standard RS232 UART is not meant for high thoughput. If it was me personally I would go with the EZ-USB solution since it is easy to use and can hit 40Mbps and higher without breaking a sweat. You could also use Nios II and the host FS, it's not quick but it will probably outrun a RS-232 UART with out any extra components besides the Nios II JTAG debugger.
0 Kudos
Altera_Forum
Honored Contributor II
332 Views

thank you for your suggestion

0 Kudos
Reply