C3 AS configuration problem

[Altera_Forum]

I used one EP3C16F484I7 and one EPCS16I8N in my design. I just designed JTAG interface on my board. I can download .sof file to the FPGA and it works well. I can also download .jic file to the EPCS16 through JTAG and “verify” successfully. But when I power up the board, the FPGA can not be configured by the EPCS16. I pull down the nCONFIG signal to reconfigure the FPGA while the board has been powered, the FPGA also can not be configured by the EPCS16. 

 VCCIO of EP3C16 for all the banks are 3.3V.   The input power rail is 5V DC, I used a 2A DC/DC regulator to generate 3.3V rail from 5V rail and two LDOs to generate 2.5V rail & 1.2V rail.   The pullup and pulldown resistors for nCONFIG, nSTATUS, nCE, CONF_DONE, TCK, TMS and TDI signals mounted correctly on the board.   The schematics of FPGA and FPGA power are attached. The power rails power up waveform and configuration signals’ waveforms were also attached.

[Altera_Forum]

Acc to the MSEL connection you have choosen AS Standard POR, that is correct for EPCS. 

Vccd used for the PLL is 1,2V correct Vcca used for the PLL is 2,5V correct JTAG Pull up / downs are correct as well as the signals nConfig, nStatutus. from the first sight at your schematics everything is OK except that you have a 1K resistor between nCE and GND. tie that signal with a jumper to GND right out of my head i think that FvM explained why a couple of weeks ago in another thread here

[Altera_Forum]

MSchmitt,thanks for your reply! 

I tried to connect the nCE to GND using a jumper, it still doesn't work.   I inspected that the nSTATUS never go high after power up or during reconfiguration.   I also inspected that the nSTATUS always remain low during configure the FPGA through JTAG.   Any other suggestions?   I have no idea about it now! help me please.