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data error!help

Altera_Forum
Honored Contributor II
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look at the picture,why CpuData is wrong,but RdBuf is right, 

assign CpuData = ( CpuDataVld &HRCW_over_flag )? {8'h00,CpuDataOut} : 16'hzzzz ; 

assign RdBuf = ( CpuDataVld &HRCW_over_flag )? CpuDataOut : 8'hzz ; 

 

note:1.cpudata is a bidirection port,but rdbuf is a reg; 

2.clock is 66mhz 

 

3.the picture is a signaltap 

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

look at the picture,why CpuData is wrong,but RdBuf is right, 

assign CpuData = ( CpuDataVld &HRCW_over_flag )? {8'h00,CpuDataOut} : 16'hzzzz ; 

assign RdBuf = ( CpuDataVld &HRCW_over_flag )? CpuDataOut : 8'hzz ; 

--- Quote End ---  

 

 

Hi, 

 

is your Signaltap capture clock synchronous to the data you try to capture ? 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

 

is your Signaltap capture clock synchronous to the data you try to capture ? 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

Sorry , 

 

maybe I was a little too fast. 

 

Is your picture a signaltap or a simulation output ? Can you zoom in so that it is possible to see all value ? 

 

Kind regards
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Sorry , 

 

maybe I was a little too fast. 

 

Is your picture a signaltap or a simulation output ? Can you zoom in so that it is possible to see all value ? 

 

Kind regards 

--- Quote End ---  

 

 

Hi, 

 

you mentioned that RdBuf is a "reg", but as far as I know you can't use "assign" for reg.  

 

assign RdBuf = ( CpuDataVld &HRCW_over_flag )? CpuDataOut : 8'hzz ; 

 

CpuData is a Toplevel port ? What is connected to this port ? 

 

assign CpuData = ( CpuDataVld &HRCW_over_flag )? {8'h00,CpuDataOut} : 16'hzzzz ; 

 

According to your assignment CpuData is only during CpuDataVld "1" = CpuDataOut. With 

CpuDataVld "0" you switch back to "z". Maybe somebody is driving the port ? 

 

Can you zoom in your traces, in orde to see what values are caaptured ? 

 

Kind regards 

 

GPK
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