Problem related to PIO component in SOPC system

Altera_Forum · ‎03-26-2010

I have a SOPC Builder system with just following components: the cpu, jtag_uart, sdram and a PIO led component. It works fine as long as there is just one led component.

When I add another PIO led component to this system and try to access either of them, I get the following error:

Verifying 00800000 ( 0%)

Verify failed between address 0x800000 and 0x80D23F

Leaving target processor paused

My SDRAM, which is also the program and data memory, is at location 0x800000.

I am using the DE2 board which has another bank of LEDs available. I have made sure all the pin assignments are correct. I have also made sure there is no address overlap between any components.

This error occurs during download so I cannot debug my program to step through it and see what is going wrong at runtime.

But, before that, the system generation in SOPC Builder, Compilation in Quartus and Building Project within Nios II IDE is smooth and no errors are returned. This is error occurs when the program downloads to the board. Any insights?

I am using Quartus II 8.0, Nios II IDE 8.0 and DE2 Board.

Thanks.

Altera_Forum · ‎03-26-2010

And I didn't mention that when I remove the new LED component, I can access the old one just fine. But when it is there I can the above-mentioned error while accessing either of them.

Altera_Forum · ‎05-19-2010

I apologize if this is obvious, but I had a simliar problem because I made a very simple mistake of not constraining my clock and reset input pins for my development board. When I would add a peripheral, the automatic assignment would move the clock somewhere else and I would get an error like you described. I used the Pin Planner to assign the clock and reset pins, and I had no more problem with it. You also have to make sure your LED outputs are assigned to the right pins for your board.

Altera_Forum · ‎05-19-2010

Have you considered the possibility of timming problem?

By adding another component, you may be changing your design timming a bit.

Altera_Forum · ‎05-20-2010

Check for shorts or shared lines on the PCB between the second PIO component and the SDRAM lines. Can you post the avalon memory map?

Altera_Forum · ‎05-20-2010

Maybe the capability of sdram is small not enough for the programme and data.