multiple clock frequency constraints

[Altera_Forum]

I am working on a design which uses a common clock, but there will be two operating modes where the clock will be at different frequencies. In the case of the lower frequency being used, all logic will be enabled, but for the higher frequency case certain portions of logic will be held in reset as they are not required for that mode. The clock will be sourced externally (the frequency change will be external). How can I constrain the clock such that the logic sections that are not required at the higher frequency are constrained to only meet the lower clock frequency, and the rest of the logic is constrained to the higher clock frequency? Would it be valid to use a gated clock to the lower frequency logic sections?

[Altera_Forum]

Hi, 

I think you could operate in this way: first of all you have to constaint your clock signal with the two different frequency, like this:  create_clock –name clk_high –period 10.0 [get_ports clk] create_clock –name clk_low –period 40.0 [get_ports clk] –add  the option -add allows you to set a double constraint in the same signal. Then set a clock exclusive group, because you use only a frequency at a time:  set_clock_groups –exclusive -group {clk_high} -group {clk_low}   For the module that works only with the low frequency, you could redefine a generated clock from the clk_low at the input pin clock of this module:   create_generated_clock -name {clk_low_module} -source [get_ports {clk}] -master_clock {clk_low} [get_pins {low_module|input_clock}] -add  That's only an idea, you have to try. bye