Please help me about of warning messages after compiling in Max+Plus Advanced:
Warning: Output pins are stuck at VCC or GND
Warning: Ignored unnecessary INPUT pin 'CLR'
Warning: Ignored unnecessary INPUT pin 'a'
Warning: Ignored unnecessary INPUT pin 'b'
this is my design in vhdl:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--------------------------------------
ENTITY mono IS PORT(
CLR, A, B : IN BIT;
Q, NQ : OUT BIT);
END mono;
--------------------------------------
ARCHITECTURE behavior OF mono IS
SIGNAL L : BIT;
BEGIN
PROCESS(CLR,A,B,L)
BEGIN
IF (CLR ='0') THEN
L <= '0';
ELSIF (A = '1' OR B = '0') THEN
L <= '0';
ELSE
--L <= '0','1' AFTER 252NS;
END IF;
Q <= L;
NQ <= NOT L;
END PROCESS;
END behavior;
----
and nothing else, but I dont' know that is wrong!
Thanks.
