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Convert a 50MHz clock into 1Hz Clock

Altera_Forum
Honored Contributor II
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Hi, 

I am working on a project that requires a counter. The ALTERA board that I am using has a 50 MHz clock on PIN N2. 

 

I wrote the following code for the counter: 

 

module counter(clock, reset, count); input clock, reset; output count; reg next_count,count; always@* begin if(count<15) next_count=count+4'd1; else next_count=count; end always@(posedge clock) begin if(reset) count<=4'd0; else count<=next_count; end endmodule  

 

I need to map the input clock to a 1 Hz clock so that the counter counts every second. But the board only has a 50 MHz clock. 

 

How can I use this 50 MHz as an input to the counter so that the counter counts every second? 

 

Please help .. 

 

Thanks!!!!
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Altera_Forum
Honored Contributor II
5,333 Views

Simple question, lots of answers. 

 

The most straighforward way is to generate a 1Hz clock by using a counter: toggle the 1Hz clock every 25_000_000 cycles of the 50Mhz clock. 

 

A couple of issues. 

First, this will require a 23 bit counter running at 50 Mhz. You can use a PLL to generate a 100 kHz clock (PLLs have lower limits) and then use a counter to generate the 1 Hz clock from the 100 kHz clock. 

 

Also, at a 1 Hz it's not really a problem but ripple clocks are best avoided and replaced by clock enables. 

 

reg [9:0] counter; 

reg enable; 

always @ (posedge clk100k) 

begin 

if (counter == 10'd0) counter <= 10'd100_000; 

else counter <= counter - 1'd1; 

 

enable <= counter == 10'd0; 

end 

 

always @ (posedge clk100k) 

begin 

if (enable) begin 

// your logic here is run only once every second 

end 

end
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Altera_Forum
Honored Contributor II
5,333 Views

 

--- Quote Start ---  

Simple question, lots of answers. 

 

The most straighforward way is to generate a 1Hz clock by using a counter: toggle the 1Hz clock every 25_000_000 cycles of the 50Mhz clock. 

 

A couple of issues. 

First, this will require a 23 bit counter running at 50 Mhz. You can use a PLL to generate a 100 kHz clock (PLLs have lower limits) and then use a counter to generate the 1 Hz clock from the 100 kHz clock. 

 

Also, at a 1 Hz it's not really a problem but ripple clocks are best avoided and replaced by clock enables. 

 

reg [9:0] counter; 

reg enable; 

always @ (posedge clk100k) 

begin 

if (counter == 10'd0) counter <= 10'd100_000; 

else counter <= counter - 1'd1; 

 

enable <= counter == 10'd0; 

end 

 

always @ (posedge clk100k) 

begin 

if (enable) begin 

// your logic here is run only once every second 

end 

end 

--- Quote End ---  

 

 

 

I was wondering if the following codes gonna work if I feed the clock input to the 50MHz clock. I ran a simulation on this code (I dont have the Altera board at home) and the report shows the code works. 

 

Please suggest... 

 

module Lab6a(clock, reset, cout); input clock, reset; output cout; reg count; //counts upto 50000000 reg cout; //original 4 bit counter always @ (posedge clock) begin if (~reset) begin if(count==50000000) begin count <= 0; cout = cout + 1; end else begin count <= count + 1; cout <= cout; end end else begin count <=0; cout <= 0; end end endmodule  

 

Thanks Again!!!
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Altera_Forum
Honored Contributor II
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to get 1Hz from 50MHz is very simple but depends on whether you want one 50% duy cycle 1Hz pulse or just one pulse of 50MHz period every 1 second. 

all you need is one bit signal that goes high or low.  

for 50% duty cycle on the 50MHz counter: 

if count is at first half 50M then raise the signal else lower it 

if you want one pulse at 50MHz period only then: 

at any one chosen count value raise the signal else lower it.
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