Dual access block ram access from nios and custom vhdl

[Altera_Forum]

First, Id like to say I'm new to using Altera FPGA's so sorry if this is very simple. I have implemented a dual access block ram in SOPC. One side goes to the nios-II core so i can read and write from my c code. I'd like the other side to be made into external ports so that I can read/write the ram from my custom vhdl code. What is the best way of doing this? Thank you!

[Altera_Forum]

you need an Avalon-Memory Mapped master to connect to the dual port RAM MM slave. take a look at custom components in SOPC Builder to make your HDL into a SOPC component, or using the component editor to make a simple MM-master that gives you access to the MM signals outside of SOPC Builder. here's a place to start: 

 http://www.altera.com/literature/hb/qts/qts_qii54005.pdf

[Altera_Forum]

These might help as good starting points for creating your own memory mastering components in SOPC Builder: 

 http://www.alteraforum.com/forum/showthread.php?t=19053 http://www.altera.com/support/examples/nios2/exm-avalon-mm.html  I would start with the first one since it's VHDL based. The second one is verilog based and has GUI customizations in the component .tcl file so it's a little bit more advanced.

[Altera_Forum]

Thank you! Using the template, I have been able to successfully read and write from vhdl to a block ram instantiated in sopc builder. I am still having a problem doing both at the same time though. What I mean by that is if I one design with read capability another design with write capability, both work fine. But when I attach two master templates (one for read, one for write) to one slave port of the block ram, the write (which works fine) interferes with the read. It seems like the read reads from the wrong address. Do I need some sort of arbitration? I thought this would be handled by the avalon logic?

[Altera_Forum]

SOPC Builder provides arbitration logic for you but you will need to handle the hazards of accessing the same address. For example if the read and write masters access address 0-1023 you will not know which master will gain arbitration to any of the locations first. If you can prevent the masters from accessing the same range at the same time then you can avoid the data hazard.