- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
a warning is displayed when perform time quest analysis(post-map):
Warning: fs~reg0|fs could not be matched with a pin My constraint: create_generated_clock -name fs -source [get_ports {clk}] -divide_by 128 [get_pins fs~reg0|fs] FYI, I have a top module that connects the clock divider and square wave(using clock enable method): square_valid sq_valid1 ( .clk(clk), .reset(reset), .sq_ena(sq_ena), .clock_ena(fs), .factor(factor), .square_1(square), .sq_valid(sq_valid) ); mod128_counter mod128count1 ( .clk(clk), .reset(reset), .fs(fs), .two_fs(two_fs) ); Besides, i have tried: [get_pins fs] [get_registers fs~reg0|fs] //fs~reg0, the name get from RTL viewer [get_nets fs] All have the same warning. I have no idea what is the problem.. thanksLink Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have found the solution and would like to share:
create_generated_clock -name fs1 -source [get_ports {clk}] -divide_by 128 [get_registers {mod128_counter:mod128count1|fs}] -add However, i have no idea on why i cant use the get_pins and get_nets. Whenever you face this kind problem, use the time quest gui to find the target. thanks
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page