ModelSim reports type mismatch in SOPC Builder generated Code

Altera_Forum · ‎03-29-2010

Hello,

I have a problem simulating my SOPC builder generated system. If I compile my design in ModelSim SE 6.5b I get the following errors:

--- Quote Start ---

# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "slave_address" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "slave_nativeaddress" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "master_nativeaddress" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/clock_crossing_0.vhd(275): Vopt Compiler exiting

--- Quote End ---

The corresponding code is the following

  --the_clock_crossing_0, which is an e_ptf_instance
  the_clock_crossing_0 : clock_crossing_0
    port map(
      ...
      master_nativeaddress(0) => clock_crossing_0_m1_nativeaddress,
      ...
      slave_address(0) => clock_crossing_0_s1_address,
      ...
      slave_nativeaddress(0) => clock_crossing_0_s1_nativeaddress,
      ...
    );

with the following port/signal definitions


                ...
                signal clock_crossing_0_m1_nativeaddress :  STD_LOGIC;
                ...
                signal clock_crossing_0_s1_address :  STD_LOGIC;
                ...
                signal clock_crossing_0_s1_nativeaddress :  STD_LOGIC;
                ...

and

component clock_crossing_0 is 
           port (
                 -- inputs:
                    ...
                    signal slave_address : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                 -- outputs:
                    ...
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                 );
end component clock_crossing_0;

I dont have problems compiling the design with Quartus II 9.1SP1. So the only workaround I see is to compile it in Quartus II and use the generated *.vho in ModelSim.

Any other suggestions ?

Thanks in advance

Altera_Forum · ‎03-29-2010

try turning off vopt, as i recall there are some incompatibilities with Quartus II and ModelSim 6.5+.

Altera_Forum · ‎03-29-2010

Yeah, this was my first though, but then I get a similar error (the types are incompatible anyway) I'm not in the office anymore, so I cant copy the error message, but I think it was vsim telling me the types are incompatible.

I have another approach now, since it's working if I start the functinal simulation as native link from Quartus II. If I find the error I'll tell you tomorrow, anyway I would appreciate if somebody already knows what I have to do to solve the problem..

Altera_Forum · ‎03-30-2010

With option -novopt I get the following error:

--- Quote Start ---

# Fatal error in Architecture europa at C:/Workspace/BB_CMMB/clock_crossing_0.vhd line 442# while elaborating region: /cmmb_remux/the_clock_crossing_0# Load interrupted

--- Quote End ---

I really dont know how to get rid of this error except fix the error manually in the file. But this can't be the solution ..

Altera_Forum · ‎03-30-2010

can you file a bug report in an SR?

Altera_Forum · ‎03-30-2010

Okay, just submitted the SR.

The only workaround I found was to add an address to the slave interface which is connected through the clock crossing bridge to the NIOS.

Altera_Forum · ‎04-01-2010

The altera support told me that this will be corrected soon.

Till it's fixed I suggest the described workaround if somebody is dealing with the same problem.