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Need help designing zero-wait-state memory.

Altera_Forum
Honored Contributor II
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Hi, I have an "economy" Nios2 core interfacing relatively slow external RAM chip. 

 

I want to help with interrupt processing performance little bit by placing exception handling code in zero-wait-state on chip memory. 

 

So far I am experiencing problems interfacing to the onchip ram. It seems I cannot achieve zero-wait-state mode. 

 

Processor is capturing data on the bus from the previous cycle. Looks like I have to add a wait state. 

 

Rith now I am feeding the ram block with the same system clock the cpu runs at. 

Should I play with generating a second clock, which is out of phase to the system clock to make it work with zero wait states? 

 

Do you know if there is an example design I can look at to learn how to do it right, with no need for any wait states? 

 

Thanks, 

Pszemol
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Altera_Forum
Honored Contributor II
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The on-chip memory components always have at least one read wait state. 

You could design your own component in HDL to create a 0 wait state memory, but it will probably have a negative impact on the system's fmax.
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Altera_Forum
Honored Contributor II
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Thanks for the reply... I guess I will deal with 1 wait state... for now. 

 

It is still much better than a 16bit external ram which is 55ns type. 

Because it is only 16bit, it takes 2x 55ns to fetch opcode from there. 

1 ws on 32bits sounds much better already. 

 

BTW - anybody knows how big the memory cpu supposed to get for this exception vector location? And what is the reason the default values have 0x20 offest? Where can I read about what code is put there in the reset/exception vectors and how big this code is? 

 

Thanks, 

Pszemol
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