- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear All,
i have designed a system which contains a dual port ram( Avalon MM slave ) one port is used to "talk" with the Nios and the other one is talking to a Multiplexed Addres bus(PPI) which i made as an Avalon MM Master. As soon as I perform a read from the PPI. I assert the avm_master_address, avm_master_read like described in the specification. then the data should appear on the avm_master_readdata the next clock cycle if avm_master_waitrequest is not asserted. In my case the avm_master_waitrequest is asserted for one clockcycle, so the data would be present the next clockcycle, which is fine by me. but the data is not present that clockcycle. it changes to the correct data after maybe 20 to 35 clockcycle and then avm_master_request is not high. What could be problem here?? picture of signaltap can be found here: h ttp://img402.imageshack.us/img402/8173/strangewaitrequest.png (need to remove the spaces )Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It's hard to tell in the signal tap capture but the master should be asserting read for two clock cycles. The first cycle the waitrequest happens to fire meaning the read has not completed until the 2nd cycle.
Note: if you use a pipelined read master (use the 'readdatavalid' signal) the fabric will not need to generate waitrequest on the first cycle of each on-chip memory read. This will effectively double your memory bandwidth assuming the master can keep up.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page