Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20640 Discussions

Exit code = 11... Device verify failure

Altera_Forum
Honored Contributor II
2,244 Views

Hi, 

 

I use Jam STAPL Player Version 2.5 to implement CPLD upgrade. 

But the program return "Exit code = 11... Device verify failure" 

1. My system is ARM cpu on Embedded Linux. 

2. I only change jam_jtag_io() to map our JTAG port. 

3. The TCK click work about 5KHz 

Suspicion: 

1. The porgram can detect IC. I think that TCK, TDI and TDO are correct. 

2. I use Quartus II program CPLD and then use Jam STAPL Player to do only verify action. The result is pass. Base on this experiment, the Jam STAPL Player verify function is correct. 

So, The TCK, TDI and TDO are correct and verify function is correct. May the program is bad. But I do know how to debug the program function. 

Below is my program message: 

 

C:\jam.exe -aprogram 001.jam -v 

Jam STAPL Player Version 2.5 (20040526) 

Copyright (C) 1997-2004 Altera Corporation 

CRC matched: CRC value = 75D4 

Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3088 

NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 9.0" 

NOTE "DATE" = "2010/03/26" 

NOTE "DEVICE" = "EPM240" 

NOTE "FILE" = "data_sw_0204b.pof" 

NOTE "TARGET" = "1" 

NOTE "IDCODE" = "020A10DD" 

NOTE "USERCODE" = "FFFFFFFF" 

NOTE "CHECKSUM" = "0016738E" 

NOTE "SAVE_DATA" = "DEVICE_DATA" 

NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A43, A92, A94, A95, A99, A100, A105, A109, A111" 

NOTE "STAPL_VERSION" = "JESD71" 

NOTE "JAM_VERSION" = "2.0" 

NOTE "ALG_VERSION" = "51" 

Device# 1 Silicon ID is ALTERA04(00) 

erasing MAXII device(s)... 

erasing MAXII UFM block... 

erasing MAXII CFM block... 

programming CFM block... 

programming UFM block... 

verifying CFM block... 

Device verify failure 

Exit code = 11... Device verify failure
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
1,007 Views

Who can help me?:confused:

0 Kudos
Altera_Forum
Honored Contributor II
1,007 Views

Hello Pandaliu, 

 

i have the same problem with the same PLD device and ARM as host. Did you have any new infos for that? 

Thanks 

 

Thomas
0 Kudos
Altera_Forum
Honored Contributor II
1,007 Views

Hi Thomas 

 

We fixed this probleam. Please fine turn one_ms_delay parameter. 

The TCK bit clock must below 1MHz. 

 

one_ms_delay /= DELAY_SAMPLES; <-- Please modify it 

:)  

Panda
0 Kudos
Altera_Forum
Honored Contributor II
1,007 Views

Hi Panda, 

 

thanks for your answer. I thought i has adjust this parameter exactly, but i measure it again and found that the timing wasn't excat enough, because the function do_wait_microseconds is called with values over 500.000!  

Now it works fine! 

 

Best regards 

 

Thomas
0 Kudos
Reply