Hard Processor System's AXI SDRAM

Altera_Forum · ‎05-19-2017

I'm trying to create Qsys project that connects a simple AXI peripheral in the FPGA to the hard processor system for the DE0-Nano-SOC dev board/Cyclone V. However, the Arria V/Cyclone V HPS IP contains some SDRAM ports that are causing problems for place-and-route further down the line: f2h_sdram0_clk, f2h_sdram0_data.

1) Why does the HPS IP need these interfaces? Isn't the HPS already connected to 1GB of hard DDR3 on the board?

2) Can these interfaces be removed?

3) If the interfaces cant be removed, is there another work around, like terminating them somehow?

Thanks,

Dave

Altera_Forum · ‎06-08-2017

1) these interfaces are to connect SDRAM to FPGA fabric: export data & clk signals to FPGA or connect in Qsys with another IPs.

2) If you desactivate these interfaces in Edit menu of HPS, then the FPGA can't read/write SDRAM directly