timing simulation with modelsim-altera

[Altera_Forum]

Hi everybody! 

 Does anyone know how I can perform timing simulation using modelsim. I have downloaded Quartus II 9.1 free suscribtion edition and free modelsim from altera website. I have a very simple design: an input port, not gate and output port. I want to see the delay between ports in modelsim wave. How can I do that??  Thanks for answers!!!

[Altera_Forum]

Hi, 

 you need to setup the NativeLink in Quartus to use ModelSim as the simulator, write a testbench.  To set it up, go to Assignments -> EDA Tools Setting -> Simulation  Then you can invoke ModelSim directly from Quartus  Tools -> Run EDA Simulation Tool  For details, look into the Quartus II handbook, there's a Chapter about ModelSim.

[Altera_Forum]

Fist, thank's for the answer. I have performed timing simulation with modelsim-altera. 

 But I can see just my code "ports" waves behavior.  I want to check for instance the delay between a logic gate input "port" and the output "pin" of this logic gate. How I can do that in modelsim?  Thanks for answers :)

[Altera_Forum]

Hi, I'm having touble with the PowerPlay tool in Quartus II. I'm a beginner to this software. I have generated the reqd vwf , vcd and saf files but when i run the PowerPlaytool i keep getting an error saying ' Successful run of Assembler reqd' . I the run the fitter and assembler from the processing/start menu , but i still receive the same error. I would be greatful if you could help me . 

 Thank You.

[Altera_Forum]

Hi shalom, 

 I saw your post.I am as novice as you were when you had postedd this . I need to carry out a worst case delay analysis for my verilog design.  I ahve compiled my deisgn and simulated it in altera modelsim.I can observe the delays in my waveform ouput.But I need to measure theprecise delay . Is therre any seting in the modelsim to obtain the timing analysis report?  Please share them as soon as possible.

[Altera_Forum]

Instead of relying on a delay (gate-level) simulation, use the TimeQuest timing analyzer along with your RTL simulation to verify your design. This is much easier to setup and use than a gate-level sim.

[Altera_Forum]

If you are checking the timing simulation to ensure delays are "what you expected", there is probably something wrong with your design

[Altera_Forum]

Hi all, 

I have a question related to this thread. When I run a gate level simulation, I never see gate delays in the Wave view. As an example, I created an 8 bit counter, and expected to see some delay from rising clock to the Q outputs. But the output transitions line up precisely with the clock transition no matter how tight I zoom in. Question: should I see typical delays that would be present in the physical device? Are there settings somewhere that I need to change?  Thanks! Tony

[Altera_Forum]

Sounds like you're running an RTL simulation, not a gate level one.

[Altera_Forum]

Tricky, well I click on the "Gate Level simulation" toolbar button in Quartus, and still not seeing any delays in the waveforms. Is there any other setting I need to make to insure a true gate level simulation? Thanks.

[Altera_Forum]

Any ideas why I'm not seeing gate delays when I run a gate level simulation??? Thanks.

[Altera_Forum]

Sorry I cant help here - I never run gate level sims (RTL simulations and timing analysis are all you need 99.99% of the time - 10+ years in industry, never needed a gate level sim). 

Why are you trying a gate level simulation? if you are relying on gate delays for timing, then you are going to run into problems. Gate level sims will only show the worst case, and in reality the timing will vary.

[Altera_Forum]

Tricky, 

I'm new to Altera (my past experience has been with Xilinx), so I'm just trying to learn Quartus and Modelsim. My method of "climbing the learning curve" is to try something and see if the results are what you would expect. I've read that a gate level sim. is supposed to show actual gate delays, but I'm not seeing it. No particular reason I need to do a gate level sim., other than it is part of the learning process. Tony

[Altera_Forum]

Hello, I am having problems with a ModelSim simulation of a program. The signals I want to simulate (with a RTL simulation) change their logic state in microseconds and I cant find the way to change the timing of the simulation. I tried to change it to 100 us and the simulation stops in 20000 ps so I cannot see anything. How can I increase the time of simulation in ModelSim

[Altera_Forum]

from the tcl consol, you can type how long you wish to run: 

 run 100 us  If it doesnt run for this long, there is a problem with the code/testbench.

[Altera_Forum]

Yes, I think that is the problem, I will try to fix it. This is the first time I have this problem. I will re-think the testbench code, thanks Tricky.

[Altera_Forum]

if you post the code, maybe we can help?

[Altera_Forum]

Hi Tony, 

 May I know what device that you were using? If you were using V series device, gate level simulation is not supported. Gate level simulation is supported on IV series and lower, and you will had to use *.sdo for it.  Usually, gate level simulation will be very slow for verification. user should use time quest instead for timing analysis.  Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation)