How to simulate and get waveform on Linux?

[Altera_Forum]

Hi, everybody! 

 I'm using quartus II 9.1 sp2 with ModelSim from altera, of which version is 9.1 sp2, on openSuSE 11.1.  Plz tell me how to get waveform. When I google it, I got information to make Vector Wave form file, but I could not get that option in "New file.."  And when I tried to use EDA simulation library compiler, I faced such problem below,  "The ModelSim-Altera software comes packaged with precompiled simulation libraries.  Do not compile simulation libraries if you are using the ModelSim-Altera software."  I set that The directory of Executable location was "/opt/altera9.1sp2/modelsim_ase/bin" and Tool name was "ModelSim".  How to solve this problem or How to simulate my verilog file.  Thanks!

[Altera_Forum]

up up! 

 If I have omit something, please ask me.  Thanks!!

[Altera_Forum]

There is no waveform editor on the linux version of Quartus, and it will dissapear in the next version on Windows. 

What you need to do is to write a test bench in (System)Verilog and run it in Modelsim.

[Altera_Forum]

Thanks a lot ! 

 But, after setting to run gate level simulator after compilation, and compiling, I got a message that the path of the EDA tool was wrong. Set the path in the page of EDA option of option dialog.  But I could not find EDA option in Tools >> option.. dialog, there are only message, internet connectivity, fonts, Processing, and so on.  I felt that I mistook the settings or the basic way of simulation.  How to get wave form from Modelsim?? Please tell me how to launch ModelSim?  Well, I have installed modelsim 9.1sp2 in /opt/altera9.1sp2/modelsim_ase/.

[Altera_Forum]

it should be in Tools > Options > General > EDA Tool Options

[Altera_Forum]

Thanks your advice, but I could not find such item. 

 I took a screenshot, that was the window, which called from Tools >> option...  http://web13.twitpic.com/img/95218343-2345ba692496c835c1afa439e80b89c3.4bdf0068-full.png (http://web13.twitpic.com/img/95218343-2345ba692496c835c1afa439e80b89c3.4bdf0068-full.png)  Have I mistaken in installing? Or version problem? Any way, I'm very in trouble, please help me...:confused:

[Altera_Forum]

i can't see your picture, but i opened up Quartus II 9.1sp1 Web Edition on Linux and i see what you mean. i am guessing you must be using Web Edition for Linux? 

 http://www.altera.com/literature/po/ss-quartus_linuxwebbeta.pdf  it looks like EDA Simulation is not yet a supported flow in the beta. you can use ModelSim-AE without NativeLink (read the Quartus II Handbook ModelSim chapter to learn how to setup a simulation without NativeLink) or you can try and add the paths to ~/.altera.quartus/quartus2.ini  just above the section called [General 9.1] i have a section:   EDA_TOOL_ENABLE_NATIVELINK_FOR_SYNPLIFY_NODE_LOCKED_LICENSE = off EDA_TOOL_PATH_MODELSIM_ALTERA = /path/to/modelsim/ae EDA_TOOL_USE_QUARTUS_EDA_PLUGIN_PATH_VARIABLE = on  try backing up your quartus2.ini then adding the above section to it.

[Altera_Forum]

Wow!Thank you! 

I could see ModelSim window. But I can not see how to get the result of simulation and just see# Load canceled in the dialog box at the foot.  Your help is great to me, please tell me what should I do next to get results?  Googling this, just I see the way "Create Vector Waveform file"...

[Altera_Forum]

Now, I could call out wave form window, and am learning about simulation function of Verilog HDL. 

 Thanks a lot! And it seems almost can do it. If I had another problem, I'll ask it perhaps.  Thx!

[Altera_Forum]

Hi, everyone! 

Now, I have run into the problem that below for 2 days:   --- Quote Start ---   Error: Can't synthesize current design -- design does not contain any logic   --- Quote End ---   But the project has two files, one is testbench, and another is real source code. Why does such problem that there are no logic happen ? What setting or/and source code is wrong ? Plz tell me what perhaps is! Thx!    --- Quote Start ---  module hogege;   reg sw1, sw2; // ???????????  wire led; // ??????   nandtest nandtest1 (sw1, sw2, led); // ?????????   initial // ????  begin  sw1<= 0;  sw2 <= 0; # 5 sw2 <= 1;   end    always begin  # 10 sw1 <= ~sw1;   end   always begin  # 16 sw2 <= ~sw2;   end     initial $monitor($stime, " sw1=%b sw2=%b led=%b", sw1, sw2, led);   endmodule  --- Quote End ---      --- Quote Start ---   `timescale 1ns / 1ps  module nandtest(input sw1, sw2, output led);    assign led = ~(sw1 & sw2); // ??????????????????   endmodule   --- Quote End ---  

[Altera_Forum]

I assume that this error comes from Quartus and not Modelsim? 

The testbench itself should only be included in the Modelsim project and the Quartus project should only contain the design that will go in the FPGA.  If you put the testbench as the top level design file in Quartus, it will see that your project doesn't have any inputs or outputs and will conclude that it doesn't need to synthesize anything.

[Altera_Forum]

Thank you your help! 

Yes, the problem (?) is Quartus's. Now I can run test-bench by following your advices.  Thanks a lot.  At last, I can start to developing Altera device ; )