Using High-Speed DDR3 Controller II with Registered DIMM

[Altera_Forum]

I'm trying to interface my Stratix IV GX with an 8GB SDRAM RDIMM using the DDR3 SDRAM High Performance Controller. How do I connect the CB[7:0] pins (the ECC check bits) of the DDR3 device to the FPGA? If I enable error checking in the controller MegaWizard, I don't get the 8 check bits the DDR3 memory device is expecting. Any ideas? 

 Thanks!

[Altera_Forum]

When you enable ECC in the PHY/controller you should just get 8 extra data bits, the PHY doesnt need to know which are ECC and which are data. So if you have a 64bit dimm and enable ECC you'll end up with a 72 bit dimm.

[Altera_Forum]

--- Quote Start ---  When you enable ECC in the PHY/controller you should just get 8 extra data bits, the PHY doesnt need to know which are ECC and which are data. So if you have a 64bit dimm and enable ECC you'll end up with a 72 bit dimm.  --- Quote End ---    When I enable error checking and correction, the MegaWizard only allows a data bus size of 40 or 72 - so you are saying that I can simply use 0-63 as my 64-bit data bus and 64-71 as my eight CB bits? Thanks for your input.

[Altera_Forum]

The IP only supports 32+8 or 64+8 bit interfaces with ECC. 

 On your typical dimm all memory chips are the same so it doesnt matter which DQS groups go where.

[Altera_Forum]

Thanks for your feedback std_logic.  

My RDIMM module has distinct CB pins but I can't find any information in the part's datasheet as to how they are actually used, other than they are used for ECC purposes. So, the RDIMM has 64 data bits and 8 ECC bits - do I simply connect the 72 DQ bits of the FPGA's DDR3 controller to combined 72 bits of the RDIMM?  Do the FPGA or the RDIMM typically care which bits are used for the ECC and which are used for DQ? Or does it not matter since they'll be written out and read back in the same manner, so they may get twisted up on writes but will be read back in the same twisted manner?  Thanks.

[Altera_Forum]

You got it at the end there. You want to keep the DQ groups +DM pin (if used) together but it doesn't matter what group it gets pinned out to as it'll be re-corrected on the way back in during a read.  

 An RDIMM or any dimm for that matter has no knowledge of ECC, the encoding is done in the controller and as far as the DIMM goes its just another chunk of data. At least this is the case with all DIMMs I have seen. Look at the components on it, does the CB pinned component look any different to the others?

[Altera_Forum]

OK great. I was confused why the Altera DDR3 controller didn't generate an explicit CB[7:0] bus like the RDIMM is expecting. However, on the RDIMM's connection diagram (in the part's datasheet), it shows the CB bits associated with DQS strobes 8 and 17, so it appears to expect the CB[7:0] data just as normal data. There isn't really any other mention of the functionality behind it all in the data sheet, however, so I'm going to treat it as a 72-bit data bus and leave it at that. As long as the DQ and DQS/DQSn pins are all grouped together they can be moved around within the FPGA in the future, anyhow. 

Thanks std_logic.