Read from a text file

[Altera_Forum]

Hello, 

I'm trying to read a text file with VHDL to generate some automatic input codes. I made a project just to test this entity, but my output is always with value 'Z'.  my text file contains only one line and the line contains this "11111111"  Observation : the cod.txt was created with QuartusII and is included to the project!  i think quartus can't open or read the file or something like that  thanks in advance   library std; library ieee; use std.textio.all; use ieee.std_logic_1164.all; entity readfile is port(clock : in std_logic; --output : out std_logic_vector(7 downto 0); output : out std_logic ); end readfile; architecture logic of readfile is --signal aux: std_logic_vector(7 downto 0); begin process(clock) variable inline:line; variable character_variable:character; variable end_of_line:boolean; file myfile:text is "cod.txt"; begin if(clock'event and clock = '1') then readline(myfile,inline); read(inline,character_variable,end_of_line); for i in 0 to 7 loop read(inline,character_variable,end_of_line); case character_variable is when '0' => output <= '0'; when '1' => output <= '1'; when others => output <= 'Z'; end case; end loop; --output <= aux; end if; end process; end logic;

[Altera_Forum]

This simple code may help 

  read_vector:process file file1 : text open read_mode is "filename.txt"; variable line1 : line; variable i : integer; begin wait until clk = '1'; readline(file1,line1); read(line1,i); data_out <= std_logic_vector(to_signed(i,10)); end process;

[Altera_Forum]

I notice several things wrong with your VHDL - I've made the comments next to the lines of code: 

 library std; library ieee; use std.textio.all; use ieee.std_logic_1164.all; There is also the package ieee.std_logic_textio that allows you to read/write directly to std_logic(vectors). It has OREAD and HREAD functions too, allowing you to read octal and hex strings.   process(clock) variable inline:line; variable character_variable:character; variable end_of_line:boolean; file myfile:text is "cod.txt"; I recommend using the '93 file handling: file : myfile : text open READ_MODE is "cod.txt";    readline(myfile,inline); read(inline,character_variable,end_of_line); for i in 0 to 7 loop read(inline,character_variable,end_of_line); case character_variable is when '0' => output <= '0'; when '1' => output <= '1'; when others => output <= 'Z'; end case; end loop; The reason you are getting 'Z' is that when you get a rising edge of the clock, it is reading all 8 characters in the same delta cycle, so time doesnt actually advance until it's finished the file. What you need to do is wait after each character read.  What is the end_of_line variable for?  if you use std_logic_texio, theres no need for reading characters, you can read directly into the output. Also, as you dont need it to be synthesisable, you can do whatever you want with regards wait statements and other useful stuff:   process --note no clock - this is important cos you need to use wait statements file myfile : text; variable inline : line; begin FILE_OPEN(myfile, "cod.txt", read_mode); readline(myfile, inline); for i in 0 to 7 loop read(inline, output); wait until rising_edge(clk); end loop; FILE_CLOSE(myfile); --so we can restart the file end process;

[Altera_Forum]

Are you trying to use the *.txt file in synthesizable FPGA code? It isn't supported by Quartus, I think.

[Altera_Forum]

Try to use .mif files instead of txt files. 

You can read more about it on the "memory initialization files" chapter on the use manual.

[Altera_Forum]

--- Quote Start ---  Try to use .mif files instead of txt files. You can read more about it on the "memory initialization files" chapter on the use manual.  --- Quote End ---    They are only good for building memories via the altsyncram megafunction. Otherwise they are pretty useless.

[Altera_Forum]

Tricky, yes you are right, but there are other file formats that native HDL can read and interpret as memory, and those are described in the same chapter of the user manual. 

 Furthermore, if we really want arbitrary file read and parsing form a filesystem, then either: - It will not be synthesizable or - it will need Nios software.  I think he wants none of them. I think we really wants a simple memory initialization file.

[Altera_Forum]

Belitos - Is this a test setup for simulation or are you trying to create a ROM for real hardware?

[Altera_Forum]

Thanks everyone for the help! 

 Tricky, I'm creating a simplified MIPS CPU with VHDL. So i want to read a file with my instructions (nop,add,sub,addi,subi,or,and,j,jr and beq) to simulate the waveform vector.  I'm deciding if i create a entity called "memory" and store the instructions there and my PC will read this memory or the PC itself will read this file.  I will examine the codes that you people posted and the comments too. and FvM i'm not using a FPGA, i will only need to generate the waveform vector!

[Altera_Forum]

Strange... 

It says i don't have the library "ieee.std_logic_textio". I'm using the Quartus II Web Edition version 9.0 So i found the library at Google but when i compile "Error (10405): VHDL error at readfile.vhd(32): can't determine type of object at or near identifier "read" -- found 0 possible types"  Observation i added the library to my project!  =(

[Altera_Forum]

--- Quote Start ---  This simple code may help    read_vector:process file file1 : text open read_mode is "filename.txt"; variable line1 : line; variable i : integer; begin wait until clk = '1'; readline(file1,line1); read(line1,i); data_out <= std_logic_vector(to_signed(i,10)); end process;  --- Quote End ---    WHen i use this code my output is 00000001 always

[Altera_Forum]

--- Quote Start ---  i'm not using a FPGA, i will only need to generate the waveform vector  --- Quote End ---   Textio works in full-featured simulators as ModelSim, but I fear, it doesn't in Quartus simulator. Please correct me, if I'm wrong.

[Altera_Forum]

I'm kinda lost right now =( 

cant make this entity read my file... i'm sad... i dont know if i beat Quartus or myself Hahaha It's been weeks trying to read that file

[Altera_Forum]

--- Quote Start ---  WHen i use this code my output is 00000001 always  --- Quote End ---     All you need is add extra statement to continuously read out on every clock edge:    read_vector:process file file1 : text open read_mode is "filename.txt"; variable line1 : line; variable i : integer; begin wait until clk = '1'; if(not endfile(file1))then readline(file1,line1); read(line1,i); data_out <= std_logic_vector(to_signed(i,10)); end if; end process;

[Altera_Forum]

You sure this will work? 

i didn't test it yet.       because in my first post i told that the file contains "11111111"   this is not a number, its a instrucion 111 <- op code 11 <- target register 11 <- source register 1 <- func bit (in this case subtration)

[Altera_Forum]

Where do you do the instruction decoding? is it in the Unit under test? if these 4 things are separate inputs you'll need yo separate them in the file with spaces. Or you could read the lot and decode it yourself in the testbench.

[Altera_Forum]

Sure you just need to add some concurrent assignments (outside of a process) 

  op_code = data_out(2 downto 0); target_reg = data_out(4 downto 3); source_reg = data_out(6 downto 5); func_bit = data_out(7);

[Altera_Forum]

--- Quote Start ---  Where do you do the instruction decoding? is it in the Unit under test? if these 4 things are separate inputs you'll need yo separate them in the file with spaces. Or you could read the lot and decode it yourself in the testbench.  --- Quote End ---     I hate a CPU in another project... i just want to be able to read the file, so i can decode the instructions but its been difficult to read the file =( i will try the Kaz's new code and see if i can read it. and Tricky. my quartus doesnt have the std_logic_textio... is this normal?

[Altera_Forum]

The Quartus help clarifies under predefined language environment (quartus ii vhdl support):  

  --- Quote Start ---  calls to TEXTIO functions are ignored  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  The Quartus help clarifies under predefined language environment (quartus ii vhdl support):  --- Quote End ---    Why they did that? This means i can't read a text file? what kind of file i can read then?

[Altera_Forum]

You cant read any files in quartus. Quartus is meant for synthesis, not simulation. reading text files is mostly for testbenching. 

 I recommened you use modelsim instead.