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Hi. I would like to combine or package a project I created and tested (in verilog) so I can use it like an IP or as a single module in another project. For example: my top level module has other modules, assignments for timing analysis (e.g. falls paths, multicycle definitions) and *.mif memory initialization file. Now I would like to use that design in a new project and be able to change and update it's *.mif file with out directly adding all of its modules and assignments.
What is a good strategy for using other projects in this way with in your current project. Do I need Subscription version of Quartus? Any help or hints would be greatly appreciated. Thankx. Note: I'm using Quartus II v9.1 Web Edition and design is in Verilog.Link Copied
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No need for subscription edition.
Just include the same file by using relative paths, (it's better than absolute, but not a hard requirement) Make the file parameterizeble via parameters (verilog) or generics (VHDL) And that is it.
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