Nios® V/II Embedded Design Suite (EDS)
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problem with niosII

Altera_Forum
Honored Contributor II
1,034 Views

when i try to run my program as NiosII instruction set simulator this warning appear,i dont understand how to solve it: 

 

**** build of configuration debug for project farha **** 

 

make -s all includes  

compiling hello_world.c... 

linking farha.elf... 

info: (farha.elf) 39 kbytes program size (code + initialized data). 

info: 2009 kbytes free for stack + heap. 

post-processing to create ext_flash.flash 

hardware simulation is not enabled for the target sopc builder system. skipping creation of hardware simulation model contents and simulation symbol files. (note: this does not affect the instruction set simulator.) 

post-processing to create onchip_ram.hex 

build completed in 12.781 seconds 

 

what shall i do to have a result. 

i'm working with niosII ide(v9),quartus(v9),cycloneII 

:confused::confused::confused:
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Altera_Forum
Honored Contributor II
332 Views

Did u configure your sopc system pins?

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Altera_Forum
Honored Contributor II
332 Views

Not yet,how to do it?

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Altera_Forum
Honored Contributor II
332 Views

Follow this tutorial.;)

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Altera_Forum
Honored Contributor II
332 Views

Maybe you need asure the .sof is right!

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