Avalon tristate slave timing control

[Altera_Forum]

Hi, 

 I am designing an interface to byte wide Nand Flash using the avalon tristate slave interface. One issue I have run into is that the flash comes up in a slow interface timing mode until it is written with an updated timing mode command. I am using fixed wait and hold state timing on the avalon bus, but from what I can tell the Nios cannot change this timing as it was set in SOPC builder. I would like to run the interface at the higher speed once the flash is set to the new timing mode, but I need to first access it at a slower speed to change the timing mode.   Is there any way for the Nios to control the wait/hold state settings for the avalon bus? Alternatively, could I use a divided down version of the clock and a clock mux to select a slower interface speed during initialization of the flash, or will this cause other problems?   One other related item: since the tristate slave interface is 8 bits and the bus master is 32 bits, when the Nios reads the flash it always does 4 byte reads to generate a 32 bit word, even if it is only trying to read a byte. Most read operations are on a 32 bit word basis, so I like the performance improvement this gives, but there are a few cases where I would like to do a single byte read. Since the Nand flash is a sequential (streamed) interface, the extra 3 byte read cycles when reading a byte are a problem. Is there any way to force the avalon interface to only generate a single byte read cycle to the flash?

[Altera_Forum]

If your interface generates the 'busy' signal itself, then the timings can be controlled by your logic - so can be changed once the fast mode is enabled. 

If you only need writes at the slow speed, perhaps it is possible to leave the avalon MM interface running at full speed, and ensure the software doesn't do the cycles too close together.  It is the Nios cpu that always does 32bit reads (rather than specify the individual byte enables). I suspect that the only way to do a single byte transfer is to double map the flash - returning a byte in the low bits at the alternate address.

[Altera_Forum]

Keeping the write cycles separated in software would still violate the setup and pulse width timing, but I did find a solution by adding a second tristate slave interface with the required wait & hold states to operate the flash at the slow speed. I then mux the control signals to the flash. I think I will do something similar to get the single byte read functionality.

[Altera_Forum]

I was thinking that your logic would control the cycles to the flash - with some pio somewhere (or something else) to select between slow and fast cycles. 

Adding a lot of slave interfaces will make the avalon switch fabric larger - increasing fpga resourses and reducing Fmax. You could use high address bits to select the operation while still using a single avalon slave - might help.