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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

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Altera_Forum
Honored Contributor II
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Hei. 

 

I implemented a design in QuartusII. When i acces the rtl view, i see all the blocks i described, but when i acces the technology map viewer, 2 of them are missing. Also, i recive a warning that one of my output pins are stucked to gnd.  

 

Why is that? It dose not seem to be a design error of mine.
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Altera_Forum
Honored Contributor II
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It's problably a (small) issue with your design. 

It's causing your two missing blocks not to have any effect in the outputs and it's causing that pin to be stuck at zero. 

The blocks are missing because Quartus was able to determinet that they don't have any effect in the outputs and thus optimized them away. 

 

It's easier to grasp the issue if you simulate your design.
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Altera_Forum
Honored Contributor II
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I'll take another look in my code. The RTL is just fine, and that is why i don't get what is wrong. 

 

Thanks!
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Altera_Forum
Honored Contributor II
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In such cases, it's possible for the RTL to look fine.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I'll take another look in my code. The RTL is just fine, and that is why i don't get what is wrong. 

 

Thanks! 

--- Quote End ---  

 

 

 

Hi, 

 

have a look to the missing blocks in the RTL view. Do have inputs set to a fix value ? 

look to the outputs , all connected ? Are the blocks complete or only partly removed ? 

 

Kind regards 

 

GPK
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