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Hi, everyone!
I have run into the problem that below for 3 days: --- Quote Start --- Error: Can't synthesize current design -- design does not contain any logic --- Quote End --- But the project included two files, one is testbench, and another is real source code. Why does such problem (that there are no logic) happen ? What setting or/and source code is wrong ? Please tell me what perhaps is! Thx! --- Quote Start --- module hogege; reg sw1, sw2; wire led; nandtest nandtest1 (sw1, sw2, led); initial begin sw1<= 0; sw2 <= 0; # 5 sw2 <= 1; end always begin # 10 sw1 <= ~sw1; end always begin # 16 sw2 <= ~sw2; end initial $monitor($stime, " sw1=%b sw2=%b led=%b", sw1, sw2, led); endmodule --- Quote End --- --- Quote Start --- //verilog1.v `timescale 1ns / 1ps module nandtest(input sw1, sw2, output led); assign led = ~(sw1 & sw2); // I think this is logic circuit endmodule --- Quote End ---Link Copied
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The testbench code is ignored by the Quartus compiler, because it doens't support timed statements (#<timeinterval>). As a result, no logic is synthesized. Use ModelSim Altera Edition with HDL testbenches or Vector Waveform Files with Quartus Simulator.
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Thanks a lot!
I could not know that from books... Now, I boot Tool > Launch EDA Simulation Library Compiler ( because I can't make Vector wave form, Linux edition) My PC has ModelSim from altera, and set the location where modelsim installed. The dialog recognized(as ModelSim altera starter edition Oct 1 2009), and Set Library language as Verilog. Device family is Max II. But I just get such dialog any time.... --- Quote Start --- The ModelSim-Altera software comes packaged with precompiled simulation libraries. Do not compile simulation libraries if you are using the ModelSim-Altera software. --- Quote End --- What does it means? I just installed ModelSim, had not converted it at any. Please tell me what should I do ? Help please!Thx!
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